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Sponsors
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Technical Sponsor
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Program Schedule
Technical Session 1A
Monday, June 22
10:10 AM - 11:10 AM
(Salon A)
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Technical Session 1A: Best Paper Nominee Presentation I
Chair: xxx 60; 149; 169;
10:10 AM - 10:30 AM:
A 28nm RAID-on-Chip SoC Using On-Chip SRAM and Xfer-Driven Transfers
Xu Gao, Qiyu Wu, Xiaoyang Wang, Minjie Fan and Jiwu Shu
10:30 AM - 10:50 AM:
FAST: Failure-Aware Asynchronous Search with Early Termination for Physical Design
Sihang Lei, Xueyan Zhao, Yihang Qiu, Biwei Xie and Weiqiang Wang
10:50 AM - 11:10 AM:
MIBID: Model Based Fault Diagnosis on Ising Machines
Nafisa Sadaf Prova, Ahmet Efe, Abhimanyu Kumar, Chris Kim, Sachin S. Sapatnekar and Ulya R. Karpuzcu
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Technical Session 1B
Monday, June 22
10:10 AM - 11:10 AM
(Salon B)
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Technical Session 1B: Computer-Aided Design (CAD) I
Chair: xxx 173; 12; 15
10:10 AM - 10:30 AM:
A Fast and Accurate Surrogate Model for Clock-Mesh Timing Analysis
Muhammad Hadir Khan and Matthew Guthaus
10:30 AM - 10:50 AM:
THLR: A Top-down Hierarchical Logic Rewrite Framework for Xor-Majority-Inverter Graphs
Ran Zhang, Rongliang Fu, Shuo Ren, Wenxing Li, Da Wang, Fei Wang, Xiaochun Ye, Tsung-Yi Ho and Junying Huang
10:50 AM - 11:10 AM:
FastDSE: Enabling Efficient CPU Microarchitecture Design Space Exploration with FPGA Acceleration
Kaifan Wang, Jiabin Wu, Yinan Xu, Tianyi Liu, Ninghui Sun and Yungang Bao
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Technical Session 1C
Monday, June 22
10:10 AM - 11:10 AM
(Salon C)
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Technical Session 1C: Emerging Computing & Post-CMOS Technologies I
Chair: xxx 111; 148; 175
10:10 AM - 10:30 AM:
DarkFlow: Hierarchical Digital SiPM Architecture with Low-Loss Dataflow Readout for Dark Matter Detection
Zirui Wang, Aras Repond, Shawn Westerdale and Wantong Li
10:30 AM - 10:50 AM:
Device-Algorithm Co-Design with FeFETs for On-device Continual Learning
Fatima Tuz Zohora, Nicolas Ramos, Abinidhi Geethaikrishnan, Hai Li and Dhireesha Kudithipudi
10:50 AM - 11:10 AM:
ROA-Based Subharmonic Injection Locking for Oscillator-Based Ising Machines
Nicholas Sica and Baris Taskin
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Technical Session 1D
Monday, June 22
10:10 AM - 11:10 AM
(Seneca Room)
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Technical Session 1D: VLSI Circuits and Design I
Chair: xxx 34; 156; 88;
10:10 AM - 10:30 AM:
BLCIM: An Efficient Radix-16 Booth LUT-Based SRAM-CIM Architecture with Algorithm-Hardware Co-Optimization for NTT
Qianhua Li, Hongrui Meng, Yifan Wang, Chunshan Wang, Shengchao Zhou, Teng Zou, Qi Chen and Yufeng Xie
10:30 AM - 10:50 AM:
A Dynamic-Style Multi-Threshold NULL Convention Logic for High-Performance Asynchronous Systems
Zhihan Weng, Joseph Folwn, Randall Wade and Jia Di
10:50 AM - 11:10 AM:
FPGA-based Adaptive Texture-Aware Stereo Matching Accelerator for Co-axial RGB-NIR Sensors
Chenghe Zhang, Qingzeng Song, Yongjiang Xue, Weigang Kong and Fei Qiao
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Technical Session 2A
Monday, June 22
11:20 AM - 12:20 PM
(Salon A)
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Technical Session 2A: Best Paper Nominee Presentation II
Chair: xxx 177; 16; 113;
11:20 AM - 11:40 AM:
Fault Analysis of Microscaling Formats on a RISC-V SoC
Dillibabu Shanmugam and Patrick Schaumont
11:40 AM - 12:00 PM:
MPiCO: Memory-Pool-Based XPU-PIM Cluster over Optical I/O
with Load-Imbalance-Aware Assignment and
Execution-Site-Matching Mapping Strategies for MoE Inference
Zixu Li, Yinyin Lin, Chengchen Wang, Yong Wang, Haidong Tian and Xiankui Xiong
12:00 PM - 12:20 PM:
PiCASO: A Real-time Pi-Integrated Conversational AI System with Optimized LLMs
Mahsa Ardakani, Jinendra Malekar and Ramtin Zand
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Technical Session 2B
Monday, June 22
11:20 AM - 12:20 PM
(Salon B)
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Technical Session 2B: Emerging Computing & Post-CMOS Technologies II
Chair: xxx 152; 14; 32;
11:20 AM - 11:40 AM:
TLG2LUT6: Threshold Logic Mapping for Sub-Nanosecond Binary Neural Network Inference
Abdullah Sahruri and Martin Margala
11:40 AM - 12:00 PM:
HoloLUT: An Efficient LUT-Based Engine via Holistic Data Processing for Low-bit LLM Inference
Hui Wang, Weize Ma, Jinming Lu and Jun Lin
12:00 PM - 12:20 PM:
HDStream: An Energy-efficient 7.65 BTOPs/W Hyperdimensional Computing Streaming Processor
Ryan Antonio, Xiaoling Yi, Yunhao Deng, Fanchen Kong, Jun Yin and Marian Verhelst
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Special Session 1
Monday, June 22
11:20 AM - 12:20 PM
(Salon C)
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Special Session 1: Edge Intelligience I
Chair: xxx 235; 261; 254;
11:20 AM - 11:40 AM:
SpikeViT: A Memory-Efficient Mobile Spiking Vision Transform
James Seekings, Hasti Zanganeh, Brendan Reidy, Jason Eshraghian and Ramtin Zand
11:40 AM - 12:00 PM:
SENTRY: Spiking Event Reasoning for Selective Deep Inference in Event-Driven Edge Vision
Shayan Gerami, Sepehr Tabrizchi, Shaahin Angizi, Ramtin Zand and Arman Roohi
12:00 PM - 12:20 PM:
LeakSEAL: Power Side-Channel Leakage Analysis and Mitigation for Secure Edge AI Learning
Veeramani Pugazhenthi, Md Muhtasim Alam Chowdhury, Sujan Ghimire, Harish Kumar Dharavath, Parsa Mirfasihi, Nader Sehatbakhsh, Pratik Satam and Soheil Salehi
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Technical Session 2D
Monday, June 22
11:20 AM - 12:20 PM
(Seneca Room)
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Technical Session 2D: Hardware Security I
Chair: xxx 208; 30; 112;
11:20 AM - 11:40 AM:
SPHINX: A Framework for Security Primitive Hardware Identification and Extraction
Tanvir Hossain, S M Mojahidul Ahsan and Tamzidul Hoque
11:40 AM - 12:00 PM:
NetVault: A Lightweight IP Protection Framework for Inference on Embedded IoT Devices
Nathan Wiatrek, Chen Pan and Mimi Xie
12:00 PM - 12:20 PM:
EAGEL: Explainable And Generalized Structural Exploitation Against Logic Locking
Armin Darjani, Palaniappan Ramasamy, Nima Kavand and Akash Kumar
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Technical Session 3A
Monday, June 22
3:10 PM - 4:30 PM
(Salon A)
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Technical Session 3A: Testing, Reliability, Fault-Tolerance I
Chair: xxx 161; 36; 165; 190;
3:10 PM - 3:30 PM:
Revisiting Lottery Ticket Hypothesis: Toward Efficient and Robust Deep Neural Networks
Ruixuan Wang, Jinghao Wen and Xun Jiao
3:30 PM - 3:50 PM:
Reliability-Driven Sneak Path Current Modeling and Optimization for Passive Memristor Crossbar Arrays
Zhenlin Pei, Shah Zayed Riam, Kyle Mooney, Chenyun Pan, Na Gong and Jinhui Wang
3:50 PM - 4:10 PM:
Timing Matters: Delay Fault Characterization and Testing in SNN Accelerators
Osita Ukwuaba and Cory Merkel
4:10 PM - 4:30 PM:
LTTL: A Low-Overhead and Triple-Node-Upset-Tolerant Latch Design for Aerospace Applications
Zikang Ma, Zhongyu Gao, Xing Guo, Qianhui Liu, Yi Man, Huaguo Liang and Xiaoqing Wen
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Special Session 2
Monday, June 22
3:10 PM - 4:30 PM
(Salon B)
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Special Session 2: AI Across the Stack I
Chair: xxx 238; 239; 241; 253
3:10 PM - 3:30 PM:
Agentic Hardware Synthesis with CDM Supergates for Efficient Design Generation
Srija Vuppala, Yogeswar Reddy Thota, Mahathi Ellanti, Harshith Navin Lachappa, Avesta Sasan and Tooraj Nikoubin
3:30 PM - 3:50 PM:
PRISM: Pruning via Rectified-gradient Importance and Saliency Mapping — making models sparse for execution on edge
Zuxiong Tan, Ali Karkehabadi, Houman Homayoun, Tooraj Nikoubin and Avesta Sasan
3:50 PM - 4:10 PM:
SuperGate-Net: CDM-Based MAC for Scalable Neural Inference via Cross-Layer Analysis
Harshith Navin Lachappa, Yogeswar Reddy Thota, Mahathi Ellanti, Srija Vuppala and Tooraj Nikoubin
4:10 PM - 4:30 PM:
Transformers for Tabular Anomaly Detection in Hardware-Assisted Security: A Systematic and Empirical Study
Zhangying He and Hossein Sayadi
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Special Session 3
Monday, June 22
3:10 PM - 4:10 PM
(Salon C)
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Special Session 3: Edge Intelligience-II
Chair: xxx 275 276 278
3:10 PM - 3:30 PM:
Shallow Enough? A Cross-Architecture Study of Ultra-Low-Depth Neural Networks for Edge Inference
Chengwei Zhou, Haotian Yu, Shoma Yukawa, Deniz Najafi, Shaahin Angizi and Gourav Datta
3:30 PM - 3:50 PM:
Photonics-Enabled Edge Processing: A Vision for Near-Sensor Optical Intelligence
Deniz Najafi, Shaahin Angizi and Mahdi Nikdast
3:50 PM - 4:10 PM:
A Mixed-Signal Implementation of an ADC-Less Ping-Pong Temporal Front-End for Sensor-to-Photonic Processing
Goker Ariyak and Mahdi Nikdast
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Special Session 4
Monday, June 22
3:10 PM - 4:30 PM
(Seneca Room)
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Special Session 4: Agentic AI
Chair: xxx 269; 274; 277; 273
3:10 PM - 3:30 PM:
Cross-Platform Scaling of Vision-Language-Action Models from Edge to Cloud GPUs
Amir Taherin, Juyi Lin, Arash Akbari, Arman Akbari, Pu Zhao, Weiwei Chen, David Kaeli and Yanzhi Wang
3:30 PM - 3:50 PM:
CAPO: Certification-Guided Agentic Workflow for Physical Design Parameter Optimization
Zesong Jiang, Qihang Wu, Bing-Yue Wu and Jeff Zhang
3:50 PM - 4:10 PM:
Privacy-Preserving Constrained Evaluation of LLM-Generated HLS C/C++
Nuo Xu, Jinwei Tang, Zihang Chen, Xiaolin Xu, Wujie Wen, Zhenman Fang and Caiwen Ding
4:10 PM - 4:30 PM:
Lumi Agent: Autonomous Lumerical FDTD Simulation for PhotonicWaveguide Experiments
Winson Chen, Anna Capuano, Qing Gu and Caiwen Ding
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Technical Session 4A
Tuesday, June 23
10:10 AM - 11:50 AM
(Salon A)
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Technical Session 4A: VLSI Circuits and Design II
Chair: xxx 196; 4; 101; 200; 219;
10:10 AM - 10:30 AM:
Resource-Efficient DSP Slice for Embedded FPGAs Using Split-Posit Arithmetic
Arun M and Madhav Rao
10:30 AM - 10:50 AM:
Approx-L: An Error-Balanced Approximate Floating-Point Divider with Multi-Level Linear Compensation
Yao Shangshang, Huidong Ji and Chen Zuoning
10:50 AM - 11:10 AM:
Mixed-precision Neural Networks on RISC-V CPU with Reconfigurable SIMD Instruction Extension via eFPGA
Zixin Yang, Yanze Li, Zhichao Wei, Jian Wang and Jinmei Lai
11:10 AM - 11:30 AM:
A Resource-Efficient FPGA Accelerator for SeedHit Pre-Alignment Filter
Priyanka Agarwal, Vaishnavi Sharma and Madhav Rao
11:30 AM - 11:50 AM:
HPAL: High-Performance Adiabatic Logic in the GHz Regime for Energy-Efficient Computing
Milad Tanavardi Nasab and Himanshu Thapliyal
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Technical Session 4B
Tuesday, June 23
10:10 AM - 11:50 AM
(Salon B)
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Technical Session 4B: Computer-Aided Design (CAD) II
Chair: xxx 182; 25; 69; 49; 61;
10:10 AM - 10:30 AM:
GeoRoute: Signoff-Clean Analog Routing via Pin-Aligned Graph Construction for Robust Pin Access
Pan Jiakai, Wang Wenjia, Huang Wenjun, Shen Shengzhi, Wang Yuhe and Hu Jianguo
10:30 AM - 10:50 AM:
GoG-Predict: IR-aware Path Waveform Prediction with Structural Entity Interaction Learning
Jiajie Xu, Yanglong Mao, Ziyue Han, Yunfan Zuo, Chenpu Shi, Yaning Jia, Hao Yan and Longxing Shi
10:50 AM - 11:10 AM:
CERT: A Curved Escape Routing Framework for High-Speed Differential Pairs in Dense BGA Packages
Weiqing Ji, Boxuan Xu, Hongli Dai, Chaojie Liu, Mingyang Kou and Hailong Yao
11:10 AM - 11:30 AM:
Integrated Track Assignment and Detailed Routing for Enhanced Triple Patterning Lithography
Chengkai Wang, Weiqing Ji, Mingyang Kou, Li Fei, Nengyong Zhu and Hailong Yao
11:30 AM - 11:50 AM:
A Co-optimization Framework for Resolving Via Coloring Conflict in Multiple Patterning Lithography
Junqi Wang, Haodong Lu, Jianli Chen and Kun Wang
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Technical Session 4C
Tuesday, June 23
10:10 AM - 11:30 AM
(Salon C)
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Technical Session 4C: VLSI for Artificial Intelligence (AI) II
Chair: xxx 89; 174; 31; 176;
10:10 AM - 10:30 AM:
SpiKint: Native Full-Integer Spiking Neural Networks Training with an Efficient CIM-based Accelerator
Peilin Chen and Xiaoxuan Yang
10:30 AM - 10:50 AM:
DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
Xingzhen Chen, Zhuoping Yang, Jinming Zhuang, Shixin Ji, Sarah Schultz, Zheng Dong, Weisong Shi and Peipei Zhou
10:50 AM - 11:10 AM:
ATSGRU: Attention-Sparse Gated Recurrent Unit for Computationally Efficient Wideband Digital Predistortion of Quadrature Digital Power Amplifiers
Jiayu Yang, Wending Zhao, Zijian Huang, Yinyin Lin, Yun Yin and Hongtao Xu
11:10 AM - 11:30 AM:
MRAM-MoE: Efficient Inference of Mixture-of-Experts LLMs with MRAM Chiplet-based Accelerators
Md Tanjimur Rahman, Md Asef and Mehdi Sadi
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Technical Session 4D
Tuesday, June 23
10:10 AM - 11:30 AM
(Seneca Room)
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Technical Session 4D: Hardware Security II
Chair: xxx 203; 37; 45; 68;
10:10 AM - 10:30 AM:
METAttack: Quantifying the Vulnerabilities of Metadata Bit Flips in N:M Sparse Models
Qiang Fu and Wenfeng Zhao
10:30 AM - 10:50 AM:
Successive Bipolar Boolean Masking Scheme for SAR ADC Power Side-Channel Protection
Chengzhang Luo and Qiaochu Zhang
10:50 AM - 11:10 AM:
AXI Marks the Spot: Towards Automated Reverse Engineering in SoC Netlists
Arjun Suresh, Nils Albartus and Daniel Holcomb
11:10 AM - 11:30 AM:
Bridging Backscattering and On-chip EM Sensing for Golden-Model Free Hardware Trojan Detection
Moyao Huang, Hanqiu Wang, Shuo Wang and Domenic Forte
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Technical Session 5A
Tuesday, June 23
2:40 PM - 4:00 PM
(Salon A)
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Technical Session 5A: IoT and Smart Systems
Chair: xxx 7; 1; 145; 131;
2:40 PM - 3:00 PM:
TimeDrift: Silicon-Validated Aging-Aware Timing Margin Prediction and Adaptive Test for 16 nm FinFET FPGAs
Saher Elsayed
3:00 PM - 3:20 PM:
SlackMap: A Taxonomy-Driven Framework for Systematic FPGA Timing-Power Co-Optimization
Saher Elsayed
3:20 PM - 3:40 PM:
Intelligent UAV Coordination for Data Freshness in Energy-Harvesting IoT Networks
Mason Conkel, Wen Zhang, Mimi Xie, Yufang Jin, Wenlu Wang and Chen Pan
3:40 PM - 4:00 PM:
ReCQ: Residual Compensation for Quantized Convolutional Neural Networks
Mohammadreza Mohammadi, Matthew Grenier and Ramtin Zand
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Technical Session 5B
Tuesday, June 23
2:40 PM - 4:00 PM
(Salon B)
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Technical Session 5B: Emerging Computing & Post-CMOS Technologies II
Chair: xxx 38; 71; 140; 206;
2:40 PM - 3:00 PM:
NOVA-PIM: Noise-Aware Hyperdimensional Processing in Memory with Optimized Vector Allocation and Minimal ADCs
Keming Fan, Chang Eun Song, Xuan Wang, Tajana Rosing and Mingu Kang
3:00 PM - 3:20 PM:
CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation
Sohan Salahuddin Mugdho, Md. Shahedul Hasan, Brahmdutta Dixit, Yang Lv, Jian-Ping Wang and Cheng Wang
3:20 PM - 3:40 PM:
TRACK: Robust Path-based In-Memory Computing for Efficient Execution of Boolean Logic
Venkata Nithin Kamineni, Jinam Modasiya, Nathaniel Cady and Rickard Ewetz
3:40 PM - 4:00 PM:
Structure-Aware Quantum Circuit Partitioning via Reinforcement Learning for Efficient Re-Synthesis
Mohammad Walid Charrwi, Christian Rasmussen, Ed Younis, Wibe Albert De Jong and Samah Saeed
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Special Session 5
Tuesday, June 23
2:40 PM - 4:00 PM
(Salon C)
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Special Session 5: AI Across the Stack II
Chair: xxx 263; 264; 246; 258;
2:40 PM - 3:00 PM:
HALO: A Typed Multi-View Graph Abstraction for RTL and Netlist Learning
Kevin Immanuel Gubbi, Mohammadnavid Tarighat, Brinda Puri, Mahdi Pirayesh Shirazi Nejad, Setareh Rafatirad and Houman Homayoun
3:00 PM - 3:20 PM:
Lightweight Cross-Device Sleep Tracking on the WeBe Wearable Platform
Wei Shao, Ehsan Kourkchi, Krishi Shah, Zequan Liang, Setareh Rafatirad and Houman Homayoun
3:20 PM - 3:40 PM:
Scalability Analysis of Quantum Models for Stress and Emotion Detection
Md. Saif Hassan Onim, Travis Humble and Himanshu Thapliyal
3:40 PM - 4:00 PM:
Hybrid Quantum-Classical Optimization for MRI-Based Detection of Alzheimer's Disease and Related Dementias
Sounak Bhowmik and Himanshu Thapliyal
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Special Session 6
Wednesday, June 24
10:10 AM - 11:50 AM
(Salon A)
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Special Session 6: Emerging Hardware
Chair: xxx 236; 262; 251; 243; 257;
10:10 AM - 10:30 AM:
Neuromorphic Computing Systems Based on Parallel and Nonlinear IT Memristors
Harshvardhan Uppaluru, Jinhui Wang, Sundar Kunwar and Aiping Chen
10:30 AM - 10:50 AM:
Rethinking the Potential of Layer Freezing for DNN Training Efficiency
Chence Yang, Ningxi Cheng, Ci Zhang, Lei Lu, Qitao Tan, Sheng Li, Ao Li, Xulong Tang, Shaoyi Huang, Jinzhen Wang, Guoming Li, Jundong Li, Xiaoming Zhai, Jin Lu, Jinhui Wang and Geng Yuan
10:50 AM - 11:10 AM:
Hardware-Early-in-the-Loop for Edge AI
Isaac Arnold and Na Gong
11:10 AM - 11:30 AM:
Portable Breath Acetone Sensing System with Embedded Machine Learning for Non-Invasive Diabetes Monitoring
Md Hasib Fakir, Md Fuyad Al Masud, Na Gong and Danling Wang
11:30 AM - 11:50 AM:
A Homeostatic Plasticity-Enabled CMOS Neuron for Energy-Efficient Neuromorphic Application
Soumya Swaraj Mondal, Mohammad Nadji-Tehrani, Md Humaun Kabir, Nishith Nirjhar Chakraborty and Hritom Das
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Special Session 7
Wednesday, June 24
10:10 AM - 11:50 AM
(Salon B)
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Special Session 7: Computer Vision
Chair: xxx 245; 255; 234; 237; 250;
10:10 AM - 10:30 AM:
Semantic Smoothing via Novel View Synthesis for Robust SAR Image Classification
Daniel Brignac, Fengwei Tian, Banafsheh Latibari, Abhijit Mahalanobis and Ravi Tandon
10:30 AM - 10:50 AM:
Lightweight SAR Ship Detection via Contrastive Distillation
Surendar Devasundaram, Banafsheh Saber Latibari and Abhijit Mahalanobis
10:50 AM - 11:10 AM:
FAR: Function-preserving Attention Replacement for IMC-friendly Inference
Yuxin Ren, Maxwell Collins, Miao Hu and Huanrui Yang
11:10 AM - 11:30 AM:
CLS-LCR: Classification Subspace Learning with Learnable Categorical Regularization in Forward Forward Networks
Ali Karkehabadi, Zuxiong Tan, Tooraj Nikoubin, Houman Homayoun and Avesta Sasan
11:30 AM - 11:50 AM:
Frame Skipping Architecture for Video-Language Model Acceleration
Haoxuan Shan, Chiyue Wei, Cong Guo, Yuzhe Fu, Tian Liang, Hai Li and Yiran Chen
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Special Session 8
Wednesday, June 24
10:10 AM - 11:50 AM
(Salon C)
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Special Session 8: Reliable Quantum
Chair: xxx 240; 248; 249; 260; 272;
10:10 AM - 10:30 AM:
Uncertainty Quantification Driven Benchmarking and Characterization of Noisy Quantum Backends: A VQE Case Study
Priyabrata Senapati, Waylon Luo, Bo Peng and Qiang Guan
10:30 AM - 10:50 AM:
ML-Enabled FPGA Framework for Fast Quantum State Discrimination in Mid-Circuit Measurement Regimes
Neel Vora, Yilun Xu, Akel Hashim, Neelay Fruitwala, Nam Nguyen, Noah Goss, Jan Balewski, Birgitta Whaley, Irfan Siddiqi, Vp Nguyen and Gang Huang
10:50 AM - 11:10 AM:
Error Mitigation in Dynamic Circuits for Hamiltonian Simulation
Sumeet Shirgure and Siyuan Niu
11:10 AM - 11:30 AM:
Backdoor Threats in Variational Quantum Circuits: Taxonomy, Attacks, and Defenses
Lei Jiang and Fan Chen
11:30 AM - 11:50 AM:
Stability and Reproducibility in Heuristic Unitary Synthesis for Quantum Circuits
Christian Rasmussen, Jason Perez, Ed Younis, Wibe Albert De Jong and Samah Saeed
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Technical Session 7A
Wednesday, June 24
2:20 PM - 3:40 PM
(Salon A)
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Technical Session 7A: VLSI Circuits and Design III
Chair: xxx 64; 194; 22; 79;
2:20 PM - 2:40 PM:
CompactDAQ: Compact Data Acquisition for Pulse-Shape Discrimination
Prince John, Roger Chamberlain, George Engel, Jeremy Koertzen, A. B. M. Rafi Sazzad, Jingke Xu, Jonathan Elson and Lee Sobotka
2:40 PM - 3:00 PM:
Resource-Efficient DSP Slice for Embedded FPGAs Using Split-Posit Arithmetic
Arun M and Madhav Rao
3:00 PM - 3:20 PM:
GUPrecision: Group-Wise Uniform Precision Accelerator for Depthwise Separable Convolution using Hardware-Algorithm Co-Design
Yi Chen, Jie Lou, Malte Wabnitz and Tobias Gemmeke
3:20 PM - 3:40 PM:
Vector Value Prediction with Element-wise Stride Compression
Yanmeng Huang, Ling Yang, Yuanhu Cheng, Junhui Wang, Quan Deng, Junbo Tie, Yongwen Wang, Hai Zhong and Libo Huang
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Technical Session 7B
Wednesday, June 24
2:20 PM - 3:40 PM
(Salon B)
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Technical Session 7B: Computer-Aided Design (CAD) III
Chair: xxx 100; 212; 10; 17;
2:20 PM - 2:40 PM:
An Agile Design Framework for Resource-Efficient and Parameterizable Edge ISPs
Xitong Jiang, Qingzeng Song, Yongjiang Xue, Weigang Kong, Fei Qiao and Mingze Sun
2:40 PM - 3:00 PM:
μ-ORCA: Optimizing Acceleration for Microsecond-Scale Deep Neural Network Inference on ACAP
Shixin Ji, Jinming Zhuang, Zhuoping Yang, Xingzhen Chen, Wei Zhang and Peipei Zhou
3:00 PM - 3:20 PM:
AADBP: Automated Anomaly Detection Method for Biochemical Protocols in Continuous-Flow Microfluidic Biochips
Bowen Liu, Yuhan Zhu, Genggeng Liu and Xing Huang
3:20 PM - 3:40 PM:
PIM-FW: Hardware-Software Co-Design of All-pairs Shortest Paths in DRAM
Tsung-Han Lu, Zheyu Li, Minxuan Zhou, John Hsu and Tajana Rosing
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Special Session 9
Wednesday, June 24
2:20 PM - 3:20 PM
(Salon C)
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Special Session 9: Scalable Quantum
Chair: xxx 265; 266; 268;
2:20 PM - 2:40 PM:
Multi-Agent Control Planes for Quantum Networks: A Scalable Architecture for Autonomous Quantum Internet Management
Mariam Kiran
2:40 PM - 3:00 PM:
Survey on Anomaly-Driven Fuzzing
Sai Manoj Pudukotai Dinakarrao
3:00 PM - 3:20 PM:
CRISP: Control-Realization Integrity and Sequence Profiling
Navnil Choudhury, Ifana Mahbub and Kanad Basu
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Technical Session 8A
Wednesday, June 24
3:50 PM - 5:10 PM
(Salon A)
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Technical Session 8A: Computer-Aided Design (CAD) IV
Chair: xxx 129; 192; 213; 128
3:50 PM - 4:10 PM:
An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion
Paolo Pedroso, Lee-Way Wang and Matthew Guthaus
4:10 PM - 4:30 PM:
FAPlace: Joint Optimization of Chiplet Placement and Interposer Footprint for 2.5D Systems
Yubo Hou, Sezin Kircali Ata, Gen Liang Lim, Richard Chang, Mihai Dragos Rotaru, Rahul Dutta and Ashish James
4:30 PM - 4:50 PM:
VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation
Yiting Wang, Guoheng Sun, Wanghao Ye, Gang Qu and Ang Li
4:50 PM - 5:10 PM:
Etch-Explorer: A Robust Bayesian Optimization Framework for Stringent Constrained Plasma Etching
Yujie Zhang, Xiao Yang, Kang Zhao and Jianwang Zhai
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Technical Session 8B
Wednesday, June 24
3:50 PM - 4:50 PM
(Salon B)
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Technical Session 8B: VLSI for Artificial Intelligence (AI) III
Chair: xxx 18; 181; 179;
3:50 PM - 4:10 PM:
LightningRMS: A High-Throughput Mixed-Precision RMSNorm Accelerator for Transformer Inference
Yusuf Sur and Ozcan Ozturk
4:10 PM - 4:30 PM:
AsymVPU: A Scalable and Area-Efficient Vector Architecture via Intra-Lane Asymmetry and Hierarchical Co-Design
Junzhe Jing, Bowen Liu, Feng Min, Ying Wang and Yinhe Han
4:30 PM - 4:50 PM:
An Energy-Efficient and End-to-End Keyword Spotting Processor Using 3D Broadcast Sparse Computing Array and Hybrid Sparsity Strategy Pruning
Jianbiao Xiao, Hengxin Wang, Chiyu Zou, Yangning Hu and Jun Zhou
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Technical Session 8C
Wednesday, June 24
3:50 PM - 5:10 PM
(Salon C)
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Technical Session 8C: Hardware Security III
Chair: xxx 26; 58; 59; 178
3:50 PM - 4:10 PM:
Obfuscation and IP Piracy Detection in Approximate Circuits
Lukas Sekanina and Vojtech Mrazek
4:10 PM - 4:30 PM:
Logic Locking with Diffusion
Levent Aksoy, Marziye Pandi, Muhammad Sohaib Munir and Sedat Akleylek
4:30 PM - 4:50 PM:
From Authenticated Encryption to Hash: A Comprehensive Design Space Exploration of the NIST Standard Ascon Family
Muhammad Sohaib Munir, Tommaso Dordoni, Levent Aksoy and Sedat Akleylek
4:50 PM - 5:10 PM:
Process Identification and PUF Design Using CMOS Inverter Nonlinearity: Demonstration via 45nm & 22nm CMOS
Aakriti Barat, Savas Kaya, Avinash Karanth, Sunaim Abdullah and Soumyasanta Laha
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Poster Session I
Monday, June 22
4:30 PM - 6:00 PM
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A Physically-aware Framework for Joint MBFF Synthesis with OPTICS-based Debanking
Benchao Zhu, Jiawei Li, Yang Liu, Jianli Chen and Keren Zhu
From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
Manfred Schlägl, Jonas Reichhardt and Daniel Grosse
MP-FTRouter: Fault-Tolerant Routing for Multi-Port Fully Programmable Valve Array Using Deep Reinforcement Learning
Shiyi Ding, Yuhan Zhu, Yanggeng Fu and Genggeng Liu
Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
Weimin Fu, Zeng Wang, Minghao Shao, Ramesh Karri, Muhammad Shafique, Johann Knechtel, Ozgur Sinanoglu and Xiaolong Guo
Architectural Design of Control Logic for Continuous-Flow Microfluidic Biochips Considering Channel Straightness
Zuzhao Ma, Huayang Cai, Zhisheng Chen, Genggeng Liu and Xing Huang
SWIPER: A Sliding-Window-Based Progressive ILP for Scalable Escape Routing of Chiplet Interconnects
Ningkang Hao, Haochang Tian, Yue Li, Pin Lv, Weiqing Ji and Hailong Yao
N for One: Reticle-Reuse-Driven Routing for Silicon Interposers
Xiaokun Lin, Yujie Wang, Lang Feng, Jixiang Zhu, Xupengkai Lu, Ying Wang, Fengwei Dai and Yinhe Han
OpenCL-based Deeply Pipelined HLS Implementation for Iterative Graph Applications
Kenan Cagri Hirlak, Smail Niar and Ozcan Ozturk
Structural Timing-Aware Circuit Partitioning with Feasibility Constraints for Multi-Chiplet Design
Hengyuan Zhang, Kanglin Tian, Zirui Li, Jianwang Zhai, Xiuli Fu and Kang Zhao
CryoBoost: A 40nm Cryogenic-CMOS Matrix Multiplication Accelerator for Energy Efficient Computing
Rakshith Saligram, Samuel Spetalnick, Brian Crafton, Muya Change, Alec Norlund, Joshua Gess, R Nagimov and Arijit Raychowdhury
SELSA: SDD-Based Efficient Logic Synthesis of Adiabatic Circuits
Joseph Clark and Himanshu Thapliyal
Quantum Probabilistic Label Refining: Enhancing Label Quality for Robust Image Classification
Fang Qi, Lu Peng and Zhengming Ding
SATurn: A Low-Power FeFET Crossbar Architecture for Solving Boolean Satisfiability Problems
John Maurer, Ahmed Ahmed, Parsa Khorrami and Dayane Reis
Generalized Structural Bias Analysis for Corrupt-and-Correct Logic Locking
Joseph Madera and Kyle Juretus
XcptProof: Formal Verification of CPU Exception Transient Execution Security via Leakage Contracts
Shixuan Zhang, Yujia Zhang, Kexin Gong, Hongpeng Wang, Haixia Wang and Dongsheng Wang
SVQL: SystemVerilog Query Language
Nicholas Allison and Benjamin Tan
A Unified Low-Latency ML-KEM Accelerator with Deterministic Packetization and Conflict-Free Memory Mapping
Xiangrui Jia, Qingzeng Song, Yongjiang Xue, Weigang Kong and Fei Qiao
Memory Is the Cipher: Confidential AES in Commodity DRAM
Shouzhi Fang, William C. Tegge, Chenhao Yue, Alex K. Jones and Endadul Hoque
Swift-Healer: Firmware-Reconfigurable Self-Healing for Remote Glitch-Injection on Autonomous Navigation Systems
Ali Suvizi, Joshua Iwu, Kostas Amberiadis and Guru Venkataramani
CKKS-Encrypted RBF SVM Inference with Model Encryption via Exponential Function Approximations
Michael Huang, Sin-Wei Chiu and Keshab Parhi
Microelectronics Systems Education - CHASE: A Cloud-Native Platform for Hardware Security
Rahul Magesh, Amisha Srivastava, Sharath Pendyala, Samit Miftah, Aydin Aysu and Kanad Basu
M-OKA: An Efficient Overlapfree-Karatsuba Based Montgomery Multiplier for Cryptographic Hardware
Keerthana B, Utkarsh Goyal, Prashant Garimella and Madhav Rao
Control-Flow Collapse: Exploiting Gating Logic in MoE Accelerators via Instruction-Level Fault Injection
Weimin Fu, Zelin Lu, Gang Qu and Xiaolong Guo
CHSM-Guard: Secure Boot and In-Field Firmware Updates for Chiplet-Based SiPs
Galib Ibne Haidar, Jingbo Zhou, Mark Tehranipoor and Farimah Farahmandi
SRAM DNA: Spatial Signatures in Power-Up States for Memory Family Identification
Sayan Samanta, Biswajit Ray and Aleksandar Milenkovic
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Poster Session II
Tuesday, June 23
4:00 PM - 5:30 PM
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MalHDC: A Lightweight Hyperdimensional Computing Approach to Malware Image Classification
Alaaddin Goktug Ayar and Martin Margala
Exploring the Robustness of Captioning-Based Action Anticipation Under Model Compression
Mohammed Alawad and Md Ishak
Sky to Edge-Cloud: Heterogeneous Computation Offloading for Energy-Efficient Drone Computing
Zhehang Zhang, Bharadwaj Madabhushi, Sandip Kundu and Russell Tessier
NetLossBench: A Tiered Benchmark for GNN Hardware Trojan Detectors under Partial Netlist Observations
Liangtao Dai, Yimin Gao, Melika Morsali and Mircea Stan
When Repairs Are Not Unique: Rethinking RTL Repair Benchmarks
Maisha Mastora and Dean Sullivan
FPGA-based Acceleration of LLM Inference Using Compression-Based Similarity Classification
Paul Amoruso, Richard Yarnell and Ronald DeMara
Quantization-Aware Training for Efficient Edge DNN Deployment: A Sensitivity-Driven Approach
Al Hossain Shawn and Twisha Titirsha
Orbital AI Computing: Carbon Tradeoffs Across Satellite Scale
Nisha Sarwar, Lei Jiang and Fan Chen
Efficient Hyperdimensional Monitoring for Out-of-Distribution Detection
Alaaddin Goktug Ayar and Martin Margala
DynARMic: A Dynamic ARM Instruction Counting Tool
Ayush Shashikant Pindoria and Ronald DeMara
Learning to Place Chiplets: A Multi-Objective Reinforcement Learning Approach
Richard Chang, Partha Pratim Kundu, Jun Liu, Dingjie Lu, Sezin Ata Kircali, Yubo Hou, Jie Wang, Gen Liang Lim, Sridhar Narayanaswamy, Rotaru Mihai Dragos, Rahul Dutta and Ashish James
Low-overhead Bitwise Shifting in DRAM
William C. Tegge, João Paulo C. de Lim, Benjamin F. Morris III and Alex K. Jones
ReSafe-ViT: A Reconfigurable and Reliable Accelerator for Vision Transformer Inference
Chunyuan Shen, Ke Wang and Li Yang
Learning-Assisted Adaptive Hybrid Interconnection Design for Chiplet-Based Heterogeneous Systems
Md Tareq Mahmud, Ke Wang and Ahmed Louri
Multi-Range Communication for Chiplet-Based Systems
Arvin Delavari, Amirtha Chandrasekaran and Boris Vaisband
Adaptive Post-Decoder Memory for Low-Power 360° Video
Md Humaun Kabir, Ricardo Mulino, Ali Haidous, Soumya Swaraj Mondal, Dakota Hudson, Md Sajjad Hossain, Na Gong and Hritom Das
ART: Autonomous Radar Transceiver Architecture for Cost-Optimized Satellite Radar Systems
Michael Atzmüller, Rainer Findenig, Bernhard Greslehner-Nimmervoll and Daniel Große
PoSVM: Posit-Based Accelerator for SVM-driven Edge Biomedical Image Classification
Arun M, Mihir S Kagalkar and Madhav Rao
Analysis of Area and Power Overhead for a Synthesizable 4-Phase Bundled-Data Asynchronous RISC-V Processor
Sean Jacobs, Mark Indovina and Yashaswini Suresha
Experimentation of Asynchronous Circuit Stacking for Power Management Simplification
Calvin Herbek, Jakcson McCauley, Chad Workman and Jia Di
BitPair: An Efficient 2-Bit Serial Precision-Scalable Accelerator for GEMM in Deep Neural Networks
Jinhua Li, Menghan Li, Jun Tao and Jun Han
HeteroRAGCache: Software-Hardware Co-Design for Efficient RAG Caching using Emerging Memories
Jangseon Park, Kiseok Suh, Flavio Ponzina and Tajana Rosing
STING: A Stochastic In-DRAM Accelerator for Graph Neural Networks
Salma Afifi, Bipin Thapa Magar, Ishan Thakkar and Sudeep Pasricha
AegisX: An Acceleration Framework for Moving Target Defenses to Boost Adversarial Robustness and Computational Efficiency
Wang Xingbin, Kang Li, Mingyan Zhao, Chaochao Zhang, Jun Zhang and Rui Hou
Split-Posit MAC Architectures for Efficient Neural Network Processing
Arun M and Madhav Rao
Delta-STDP: Enabling Hardware-Friendly Supervised Learning in Spiking Neural Networks
Dayou Zhang, Yue Zhou, Jiawei Fu, Xiang-Shui Miao and Yuhui He
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