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Program
Keynote 1: AI/ML, Optimization and EDA in the TILOS AI Research Institute
Slides
Andrew Kahng
Abstract:Optimization means finding the best possible solution to a given problem -- but challenges
of scale and complexity keep many real-world optimization needs beyond reach. The Institute for Learning-enabled
Optimization at Scale (TILOS) is a new National AI Research Institute led by UC San Diego in partnership with MIT,
National University, Penn, UT Austin and Yale. TILOS is sponsored by the U.S. National Science Foundation,
with partial support from Intel Corporation. The TILOS mission: make impossible optimizations possible,
at scale and in practice. This talk introduces TILOS, its research agenda, and how it aims to establish a "national nexus"
of AI and machine learning, optimization, and use domains that include integrated-circuit design and design automation.
The talk will point out directions along which the interplay of learning and optimization can boost the scaling and quality of EDA outcomes.
Bio: Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing in the Jacobs School of Engineering at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a fellow of ACM and IEEE. He was the 2019 Ho-Am Prize laureate in Engineering. He has served as general chair of DAC, ISPD and other conferences, and from 2000-2016 served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He currently serves as principal investigator of "OpenROAD" https://theopenroadproject.org/, a $17M U.S. DARPA project targeting open-source, autonomous ("no human in the loop") tools for IC implementation, and as principal investigator and director of "TILOS" (The Institute for Learning-enabled Optimization at Scale, https://tilos.ai/), an NSF AI Research Institute.
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Keynote 2: In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges
Slides
Kaushik Roy
Abstract: Traditional computing systems based on von Neumann architectures are fundamentally bottle-necked by the transfer speeds between memory and processor. With growing computational needs of today‚s application space, dominated by Machine Learning (ML) workloads, there is a need to design special purpose computing systems operating on the principle of co-located memory and processing units. Such an approach, commonly known as "In-memory computing", can potentially eliminate expensive data movement costs by computing inside the memory array itself. To that effect, crossbars based on resistive switching Non-Volatile Memory (NVM) devices has shown immense promise in serving as the building blocks of in-memory computing systems, as their high storage density can overcome scaling challenges that plague CMOS technology today. Adding to that, the ability of resistive crossbars to accelerate the main computational kernel of ML workloads by performing massively parallel, in-situ matrix vector multiplication (MVM) operations, makes them a promising candidate for building area and energy-efficient systems. However, the analog computing nature in resistive crossbars introduce approximations in MVM computations due to device and circuit level nonidealities. Further, analog systems pose high cost peripheral circuit requirements for conversions between the analog and digital domain. Thus, there is a need to understand the entire system design stack, from device characteristics to architectures, and perform effective hardware-software co-design to truly realize the potential of resistive crossbars as future computing systems. In this talk, we will present a comprehensive overview of NVM crossbars for accelerating ML workloads. We describe, in detail, the design principles of the basic building blocks, such as the device and associated circuits, that constitute the crossbars. We explore non-idealities arising from the device characteristics and circuit behavior and study their impact on MVM functionality of NVM crossbars for machine learning hardware.
Bio: Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with Texas Instruments and joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain-inspired computing (C-BRIC) funded by SRC/DARPA. Dr. Roy has published more than 800 papers in refereed journals and conferences, holds 28 patents, supervised 95 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).
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Keynote 3: Attack-Resistant Circuit Technologies for sub-5nm Secure Computing Platforms
Slides
Sanu Mathew
Abstract: Cryptographic hardware accelerators and root-of-trust circuits like True-Random-Number-Generators (TRNG) and Physically-Unclonable-Functions (PUF) have become essential components of present-day secure platforms. These circuits provide an on-die boundary within which users are given assurances that data privacy and integrity is preserved during computations and transport between storage and compute elements. The focus of hardware security engineers over the past many years has been in improving performance while reducing area and power consumption of cryptographic circuits.
This tidy scenario was disrupted by a spate of attacks on computing platforms reported in the past few years. These attacks employed techniques such as speculative side-channels, physical (power/electromagnetic) side-channels, voltage/clock glitching and fault-injection to extract embedded secrets such as encryption keys or access privileged sections of system memory.
The security community has responded to these attacks by launching research in resilient architectures and security circuits that are resistant to physical/machine-learning attacks. This talk will discuss attack-resistant encryption circuits for popular encryption workloads such as AES and RSA as well as describe PUF circuits that are resilient to powerful machine-learning attacks. While these circuits are shown to be secure against known attacks today, attackers are getting increasingly sophisticated with high resolution probes and employing advanced machine-learning techniques to subvert protection mechanisms. Security hardware designers are therefore engaged in an arms race of constantly outwitting malicious attackers while relying on continued research in energy-efficient attack-resistant security circuits.
Bio: Sanu Mathew is a Senior Principal Research Scientist with the Circuits Research Labs, Intel Corporation, where he is leads the security circuits research team. His research work focuses on energy-efficient arithmetic data-paths, side-channel resistant cryptographic HW accelerators, post-quantum crypto circuits, fully-homomorphic-encryption hardware and entropy generation circuits. He received the B.Tech. degree from the College of Engineering, Trivandrum, India in 1993, and the Ph.D. degree in Electrical Engineering from State University of New York at Buffalo in 1999. He holds 109 issued/pending patents and has authored 95 conference/journal publications. He serves as mentor for Intel & SRC-funded projects and serves on technical program committees of ISSCC, DAC, ISLPED and ARITH conferences. Sanu is a Fellow of the IEEE.
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Technical Session 1A
Monday
June 6
10:30 - 12:00
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Technical Session 1A: Hardware Security I
Chair: Ujjwal Guin
Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment
Pantea Kiaei, Zhenyuan Liu and Patrick Schaumont
Protected ECC Still Leaks: A Novel Differential-Bit Side-channel Power Attack on ECDH and Countermeasures
(Best Paper Candidate)
Tianhong Xu, Gongye Cheng and Yunsi Fei
Side-Channel Analysis of the Random Number Generator in STM32 MCUs
Kalle Ngo and Elena Dubrova
Watermarked ReRAM: A Technique to Prevent Counterfeit Memory Chips
Farah Ferdaus, Bashir Mohammad Sabquat Bahar Talukder and Md Tauhidur Rahman
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Technical Session 1B
Monday
June 6
10:30 - 12:00
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Tech Session 1B: Emerging Computing and Post-CMOS Technologies
Chair: Deliang Fan
iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations
(Best Paper Candidate)
Shien Zhu, Shiqing Li and Weichen Liu
A Novel 2T2R CR-based TCAM Design for High-speed and Energy-efficient Applications
Kangqiang Pan, Amr M. S. Tosson, Ningxuan Wang, Norman Y. Zhou and Lan Wei
MnM: A Fast and Efficient Min/Max Searching in MRAM
Amitesh Sridharan, Fan Zhang and Deliang Fan
A Scalable, Deterministic Approach to Stochastic Computing
Yadu Kiran and Marc Riedel
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Technical Session 2A
Monday
June 6
1:30 - 3:00
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Tech Session 2A: Hardware Security II
Chair: Syed Rafay Hasan
Graph Neural Network based Netlist Operator Detection under Circuit Rewriting
Guangwei Zhao and Kaveh Shamsi
Exploration into the Explainability of Neural Network Models for Power Side-Channel Analysis
Anupam Golder, Ashwin Bhat and Arijit Raychowdhury
Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware Detection
Zhangying He, Amin Rezaei, Houman Homayoun, Hossein Sayadi
A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks
Mengqiang Lu, Aijiao Cui, Yan Shao and Gang Qu
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Technical Session 2B
Monday
June 6
1:30 - 3:00
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Tech Session 2B: Computer-Aided Design (CAD)
Chair: Mst Shamim Ara Shawkat
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud and George Stamoulis
Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration
(Best Paper Candidate)
Md Imtiaz Rashid and Benjamin Carrion Schafer
A Scheduling Framework for Decomposable Kernels on Energy Harvesting IoT Edge Nodes
Sethu Jose, John Sampson, Vijaykrishnan Narayanan and Mahmut Kandemir
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
Niklas Bruns, Vladimir Herdt, Daniel Grosse and Rolf Drechsler
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Technical Session 3A
Tuesday
June 7
10:30 - 12:00
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Tech Session 3A: VLSI Design & VLSI Circuits and Power Aware Design I
Chair: Amin Rezaei
RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers
(Best Paper Candidate)
Kamil Khan, Sudeep Pasricha and Ryan Kim
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks
Rose George Kunthara, Rekha K James, Simi Zerine Sleeba and John Jose
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories
Aswathy N S, Sreesiddesh Bhavanasi, Arnab Sarkar and Hemangee K. Kapoor
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays
(Best Paper Candidate)
Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater and David Atienza
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Technical Session 3B
Tuesday
June 7
10:30 - 12:00
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Tech Session 3B: VLSI for Machine Learning and Artifical Intelligence I
Chair: Mst Shamim Ara Shawkat
Reducing power consumption using approximate encoding for CNN accelerators at the edge
Tongxin Yang, Tomoaki Ukezono and Toshinori Sato
P^3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration
Hang Xiao, Haobo Xu, Xiaoming Chen, Yujie Wang and Yinhe Han
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy
(Best Paper Candidate)
Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan and Weiqiang Liu
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse and David Atienza
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Technical Session 4A
Tuesday
June 7
1:30 - 3:00
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Tech Session 4A: Testing, Reliability and Fault Tolerance
Chair: Riadul Islam
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology
(Best Paper Candidate)
Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, Patrick Girard and Xiaoqing Wen
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications
Aibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard and Xiaoqing Wen
Radiation Hardening by Design Techniques for Mutual Exclusion Elements
Moises Herrera and Peter Beerel
An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique
Wei Xiong, Yanze Li, Changpeng Sun, Huanlin Luo, Jiafeng Liu, Jian Wang and Jinmei Lai
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Technical Session 4B
Tuesday
June 7
1:30 - 3:00
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Tech Session 4B: VLSI for Machine Learning and Artifical Intelligence II
Chair: Ramtin Mohammadizand
HDnn-PIM: Efficient in Memory Design of Hyperdimensional Computing with Feature Extraction
Arpan Dutta, Saransh Gupta, Behnam Khaleghi, Rishikanth Chandrasekaran, Weihong Xu and Tajana Rosing
Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation
Jiaqi Yang, Hao Zheng and Ahmed Louri
Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators
Wanqian Li, Yinhe Han and Xiaoming Chen
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference
Jun Zeng, Mingyang Kou and Hailong Yao
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Technical Session 5A
Wendesday
June 8
10:30 - 12:00
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Tech Session 5A: Hardware Security III
Chair: Ahmad Salman
HELPSE: Homomorphic Encryption-based Lightweight Password Strength Estimation in a Virtual Keyboard System
Michael Cho, Keewoo Lee and Sunwoong Kim
Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging
Ruchika Gupta, Vedika J. Kulkarni, John Jose and Sukumar Nandi
A Semi-formal Information Flow Validation for Analyzing Secret Asset Propagation in COTS IC Integrated Systems
Xingyu Meng, Mahmudul Hasan, Kanad Basu and Tamzidul Hoque
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Technical Session 5B
Wendesday
June 8
10:30 - 12:00
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Tech Session 5B: VLSI Design & VLSI Circuits and Power Aware Design I
Chair: Sunwoong (Sunny) Kim
MI2D: Accelerating Matrix Inversion with 2-Dimensional Tile Manipulations
Lingfeng Chen, Tian Xia, Wenzhe Zhao and Pengju Ren
Design and Evaluation of In-Exact Compressor based Approximate Multipliers
Prashanth H C, Soujanya S R, Bindu G Gowda and Madhav Rao
LEAD: Logarithmic Exponent Approximate Divider For Image Quantization Application
Omkar Ratnaparkhi and Madhav Rao
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Special Session 6A
Wednesday
June 8
1:30 - 3:00
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Special Session 6A: Machine Learning and Hardware Attacks
Chair: Hassan Salmani
Fault-Injection Based Chosen-Plaintext Attacks on Multicycle AES Implementations
Yadi Zhong and Ujjwal Guin
The Improved COTD Technique for Hardware Trojan Detection in gate-level netlist
Hassan Salmani
Hands-On Teaching of Hardware Security for Machine Learning
Ashley Calhoun, Erick Ortega, Ferhat Yaman, Anuj Dubey and Aydin Aysu
Security Aspects of Quantum Machine Learning: Opportunities, Threats and Defenses
Satwik Kundu and Swaroop Ghosh
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Special Session 6B
Wednesday
June 8
1:30 - 3:00
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Special Session 6B: Application-oriented Hardware Security Challenges and Solutions
Chair: Sai Manoj Pudukotai Dinakarrao
Hardware Security in Advanced Manufacturing
Mohammad Monjur, Joshua Calzadillas, Mashrafi Kajol and Qiaoyan Yu
Resiliency in Connected Vehicle Applications: Challenges and Approaches for Security Validation
Srivalli Boddupalli, Richard Owoputi, Chengwei Duan, Tashfique Choudhury and Sandip Ray
Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms
Weimin Fu, Honggang Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz and Xiaolong Guo
Ran$Net: An Anti-Ransomware Methodology based on Cache Monitoring and Deep Learning
Xiang Zhang, Ziyue Zhang, Ruyi Ding, Cheng Gongye, Adam Ding and Yunsi Fei
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Special Session 7A
Wednesday
June 8
3:30 - 5:00
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Special Session 7A: Machine Learning-Aided Computer-Aided Design
Chair: Sai Manoj Pudukotai Dinakarrao
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis
Tanmoy Chowdhury, Ashkan Vakil, Banafsheh Saber Latibari, Seyed Aresh Beheshti, Ali Mirzaeian, Xiaojie Guo, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, Ioannis Savidis, Liang Zhao and Avesta Sasan
CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware Detection
Sreenitha Kasarapu, Sanket Shukla, Rakibul Hassan, Avesta Sasan, Houman Homayoun and Sai Manoj Pudukotai Dinakarrao
Survey of Machine Learning for Electronic Design Automation
Kevin Immanuel Gubbi, Sayed Aresh Beheshti-Shirazi, Tyler Sheaves, Soheil Salehi, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad, Avesta Sasan and Houman Homayoun
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Panel Session 1
Monday
June 6
3:00 - 4:00
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Panel Session 1: Security assurance in modern SoCs with applications to automotive and industrial security
Organizer: Jeyavijayan (JV) Rajendran, Texas A&M University
Panelist:
Robert Narumi, Rayethon Technologies
Peter A. Beerel, University of Southern California
Lang Lin, Ansys Inc.
Rosario Cammarota, Intel
Ian Land, Synopsys Aerospace and Defense
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Panel Session 2
Monday
June 6
3:00 - 4:00
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Panel Session 2: Non-Volatile Devices in ML, Security, and IoT Applications
Moderator: Ronald DeMara
Panelist:
Nader Bagherzadeh (UCI)
Puneet Gupta (UCLA)
Alex Jones (Pitt)
Himanshu Thapliyal (UTK)
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MSE Workshop 7B
Wendesday
June 8
3:30 - 5:00
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MSE Workshop 7B: Microelectronic Systems Education Workshop
Chair: Jennifer Hasler
Embedded Systems Education in the 2020s: Challenges, Reflections, and Future Directions
Sudeep Pasricha
A Tutorial-style Single-cycle Fast Fourier Transform Processor
Alec Vercruysse, Weston Miller, Joshua Brake and David Harris
Enhancing Information Security Courses With Remotely Accessible Side-Channel Analysis Setup
Abubakr Abdulgadir, Jens-Peter Kaps and Ahmad Salman
A Senior-Level Analog IC Design Course built on Open-Source Technologies
Jennifer Hasler
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Poster Session 1
Monday
June 6
4:30 - 6:00
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Poster Session 1
Hardware Security:
On Attacking Locking SIB based IJTAG Architecture
Gaurav Kumar, Anjum Riaz, Yamuna Prasad and Satyadev Ahlawat
Protecting Deep Neural Network Intellectual Property with Architecture-Agnostic Input Obfuscation
Brooks Olney and Robert Karam
Inter-Architecture Portability of Artificial Neural Networks and Side Channel Attacks
Manoj Gopale, Gregory Ditzler, Roman Lysecky and Janet Roveda
GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking
Gagan Gayari, Dr. Chandan Karfa and Prithwijit Guha
Distributed Logic Encryption: Essential Security Requirements and Low-Overhead Implementation
Raheel Afsharmazayejani, Hossein Sayadi and Amin Rezaei
An Oracle-Less Machine-Learning Attack against Lookup-Table-based Logic Locking
Kaveh Shamsi and Guangwei Zhao
Hardware Trojan Insertion Using Reinforcement Learning
Amin Sarihi, Ahmad Patooghy, Peter Jamieson and Abdel-Hameed A. Badawy
LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural Networks
Tolulope A. Odetola, Faiq Khalid and Syed Rafay Hasan
ENTANGLE: an Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks
Armin Darjani, Nima Kavand, Shubham Rai, Mark Wijtvliet and Akash Kumar
RAFeL- Robust and Data-Aware Federated Learning-inspired Malware Detection in Internet-of-Things (IoT) Networks
Sanket Shukla, Gaurav Kolhe, Houman Homayoun, Setareh Rafatirad and Sai Manoj Pudukotai Dinakarrao
Efficient Method for Timing-based Information Flow Verification in Hardware Designs
Khitam Alatoun and Ranga Vemuri
Computer-Aided Design (CAD):
Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement
Zhongdong Qi, Jingchong Zhang, Gengjie Chen and Hailong You
An Efficient Maze Routing Algorithm for Fast Global Routing
Zhaoqi Fu, Wenxin Yu, Jie Ma and Xin Cheng
Optimal Region-based Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints
Jie Ma, Wenxin Yu, Zhaoqi Fu and Xin Cheng
GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN
Myong Kong, Daeyeon Kim, Minhyuk Kweon and Seokhyeong Kang
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V
Lucas Klemmer, Manfred Schlaegl and Daniel Grosse
Evolutionary Standard Cell Synthesis of Unconventional Designs
Prashanth H C and Madhav Rao
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype
Pascal Pieper, Vladimir Herdt and Rolf Drechsler
VLSI Circuits and Power Aware Design:
Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array
Varun Bhatnagar, Gopal Raut and Dr. Santosh K. Vishvakarma
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Poster Session 2
Tuesday
June 7
4:30 - 6:00
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Poster Session 2
Emerging Computing and Post-CMOS Technologies:
A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers
Suryansh Upadhyay, Abdullah Ash Saki, Rasit Topaloglu and Swaroop Ghosh
Would Magnonic Circuits Outperform CMOS Counterparts?
Abdulqader Mahmoud, Nicoleta Laurenciu, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana and Said Hamdioui
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits
Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan and Weiqiang Liu
MRAM-based Analog Sigmoid Function for In-memory Computing
Md Hasibul Amin, Mohammed Elbtity, Mohammadreza Mohammadi and Ramtin Zand
MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient Applications
Vishesh Mishra, Sparsh Mittal, Saurabh Singh, Divy Pandey and Rekha Singhal
Microelectronic Systems Education:
IoT-enabled soft robots: A Problem-Based Learning Module for Electrical Engineers
Prabha Sundaravadivel, Prosenjit Kumar Ghosh and Bikal Suwal
Testing, Reliability and Fault Tolerance:
Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications
Aibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui, Zhengfeng Huang, Patrick Girard and Xiaoqing Wen
Compaction of Compressed Bounded Transparent-Scan Test Sets
Irith Pomeranz
Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests
Hari Addepalli and Irith Pomeranz
VLSI for Machine Learning and Artificial Intelligence:
LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks
Amin Shafiee, Sanmitra Banerjee, Krishnendu Chakrabarty, Sudeep Pasricha and Mahdi Nikdast
Flexible and Personalized Learning for Wearable Health Applications using HyperDimensional Computing
Sina Shahhosseini, Yang Ni, Emad Kasaeyan Naeini, Mohsen Imani, Amir M. Rahmani and Nikil Dutt
An Event Based Gesture Recognition System Using a Liquid State Machine Accelerator
Jingwei Zhu, Lei Wang, Xun Xiao, Zhijie Yang, Ziyang Kang, Shiming Li and Linghui Peng
A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous Quantization
Febin Sunny, Mahdi Nikdast and Sudeep Pasricha
IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning
Lingyi Huang, Xiao Zang, Yu Gong, Chunhua Deng, Jingang Yi and Bo Yuan
MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D
Sam Engers, Cheng Chu, Dawen Xu, Ying Wang and Fan Chen
Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications
Adam Foshie, Charles Rizzo, Hritom Das, Chaohui Zheng, James Plank and Garrett Rose
VLSI Design:
HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics
Long Tan, Mingyu Yan, Xiaochun Ye and Dongrui Fan
CoSeP: Compression and Content-based Selection Procedure to improve lifetime of encrypted Non-Volatile Main Memories
Arijit Nath and Hemangee Kapoor
PrGEMM: A Parallel Reduction SpGEMM Accelerator
Chien-Fu Chen and Mikko Lipasti
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