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Keynote 1: DARPA's Data Driven Discovery of Models (D3M) and Software Defined Hardware (SDH) programs
(Water Tower AB - Floor 2, 9:00 - 10:00, Wednesday, May 23)

Moderator: Houman Homayoun, George Mason University
 
Abstract:
This talk will provide background and understand on two nationally significant DARPA programs.
 
D3M:
    Understanding the complex and increasingly data-intensive world around us relies on the construction of robust empirical models, i.e., representations of real, complex systems that enable decision makers to predict behaviors and answer “what-if” questions. Today, construction of complex empirical models is largely a manual process requiring a team of subject matter experts and data scientists. With ever more data becoming available via improved sensing and open sources, the opportunity exists to build models to speed scientific discovery, enhance Department of Defense/Intelligence Community’s intelligence, and improve United States Government logistics and workforce management, but capitalizing on this opportunity is fundamentally limited by the availability of data scientists. The Data-Driven Discovery of Models (D3M) program aims to develop automated model discovery systems that enable users with subject matter expertise but no data science background to create empirical models of real, complex processes. This capability will enable subject matter experts to create empirical models without the need for data scientists, and will increase the productivity of expert data scientists via automation.
 
SDH:
    In modern warfare, decisions are driven by information. The ability to provide useful understanding and prediction is dependent on the efficient implementation of algorithms. Today, to gain the most efficiency possible, we design and fabricate application specific integrated circuits (ASICs) to maximize the efficiency of a specific algorithm. ASICs typically cost hundreds of millions of dollars and take many years to develop, and they can perform exactly one specific algorithm. Because ASICs are so specifically tailored and costly, they are viable only for the highest priority applications. For problems that cannot afford this level of investment, compute efficiency is sacrificed by implementing solutions on general-purpose processors or field programmable gate arrays (FPGAs). Typically, this results in application implementations that are thousands of times worse than optimal. The Software Defined Hardware (SDH) program aims to develop a malleable hardware/software architecture that enables near ASIC performance without sacrificing programmability for data-intensive algorithms. SDH will enable multiple data-intensive algorithms to run at near ASIC efficiency on a single architecture without the cost, development time or single application limitations associated with ASICs or the inefficiencies associated with general purpose processing. SDH architectures can be reused for new problems and new algorithms for existing problems, and the dynamic optimization of code and hardware when input data change.
 
Bio:
    Mr. Wade Shen joined DARPA in 2014 as a program manager. His research interests include machine learning, machine translation, speech recognition and data analytics for improved human/computer interaction. Mr. Shen joined DARPA from the Massachusetts Institute of Technology, Lincoln Laboratory where he was an associate group leader in the Human Language Technology Group. Mr. Shen’s area of research involved machine translation; speech; speaker and language recognition; information extraction and prosodic modeling for both small- and large-scale applications. Prior to joining MIT Lincoln Laboratory, Wade helped found and served as chief technology officer for Vocentric Corporation, a company specializing in speech technologies for resource-constrained and embedded applications. Mr. Shen has served as the chair of Lincoln Laboratory's Advanced Concept Committee, on DARPA's Information Science and Technology (ISAT) study group and as the US technical representative for NATO's IST-078 and IST-102 speech/language processing study groups. Mr. Shen received his master's degree in computer science from the University of Maryland, College Park and his bachelor's degree in electrical engineering and computer science from the University of California, Berkeley.

Keynote 2: Self-Awareness for Heterogeneous MPSoCs: A Case Study using Adaptive, Reflective Middleware
(Water Tower AB - Floor 2, 9:00 - 10:00, Thursday, May 24)

Moderator: Baris Taskin, Drexel University
 
Abstract:
    Self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing. In the past decade this has inspired new self-aware strategies for emerging computing substrates (e.g., complex heterogeneous MPSoCs) that must cope with the (often conflicting) challenges of resiliency, energy, heat, cost, performance, security, etc. in the face of highly dynamic operational behaviors and environmental conditions. Earlier we had championed the concept of CyberPhysical-Systems-on-Chip (CPSoC), a new class of sensor-actuator rich many-core computing platforms that intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness. Unlike traditional MPSoCs, CPSoC is distinguished by an intelligent co-design of the control, communication, and computing (C³) system that interacts with the physical environment in real-time in order to modify the system’s behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). The CPSoC design paradigm enables self-awareness (i.e., the ability of the system to observe its own internal and external behaviors such that it is capable of making judicious decision) and (opportunistic) adaptation using the concept of cross-layer physical and virtual sensing and actuations applied across different layers of the hardware/software system stack. The closed loop control used for adaptation to dynamic variation -- commonly known as the observe-decide-act (ODA) loop -- is implemented using an adaptive, reflective middleware layer.
    In this talk I will present a case study of this adaptive, reflective middleware layer using a holistic approach for performing resource allocation decisions and power management by leveraging concepts from reflective software. Reflection enables dynamic adaptation based on both external feedback and introspection (i.e., self-assessment). In our context, this translates into performing resource management actuation considering both sensing information (e.g., readings from performance counters, power sensors, etc.) to assess the current system state, as well as models to predict the behavior of other system components before performing an action. I will summarize results leveraging our adaptive-reflective middleware toolchain to i) perform energy-efficient task mapping on heterogeneous architectures, ii) explore the design space of novel HMP architectures, and iii) extend the lifetime of mobile devices.
 
Bio:
    Dr. Nikil Dutt is a Chancellor's Professor of CS, Cognitive Sciences, and EECS at the University of California, Irvine. He received a PhD from the University of Illinois at Urbana-Champaign (1989). His research interests are in embedded systems, EDA, computer architecture and compilers, distributed systems, and brain-inspired architectures and computing. He has received numerous best paper awards and is coauthor of 7 books. Professor Dutt has served as EiC of ACM TODAES and AE for ACM TECS and IEEE TVLSI. He is on the steering, organizing, and program committees of several premier EDA and Embedded System Design conferences and workshops, and has also been on the advisory boards of ACM SIGBED, ACM SIGDA, ACM TECS and IEEE ESL. He is an ACM Fellow, IEEE Fellow, and recipient of the IFIP Silver Core Award.

Keynote 3: Assuring Microelectronics Innovation for National Security & Economic Competitiveness (MINSEC)
(Glessner ABC - Floor 3, 12:00 - 1:10, Thursday, May 24)

Moderator: Houman Homayoun, George Mason University
 
Abstract:
    The Office of the Deputy Assistant Secretary of Defense for Systems Engineering launched an initiative in Fiscal Year (FY) 2017 in support of trusted and assured access to advanced semiconductor technology for the Department of Defense (DoD) as well as the broader United States Government. The initiative has three main elements: (1) development of an alternate trusted photomask capability to preserve long-term trusted access and protection of Intellectual Property, (2) enhanced verification and validation activities at key government laboratories and the promotion of industry best practices and commercial standards in the areas of microelectronics trust and assurance, and (3) the development and transition of technologies in support of a new trust and assurance approach. In recognition of critical near term needs, the DoD requested additional funding in FY 2018 to address gaps in availability, access, and assurance including an initial investment in next generation disruptive microelectronics research and development to maintain U.S. technological edge in critical technology and the marketplace. This presentation will describe these efforts and discuss their status and the overarching management approach.
 
Bio:
    Dr. Jeremy Muldavin received his BSE in Engineering Physics and his MSE and PHD in Electrical Engineering with a major in Electromagnetics and a minor in Communications. He has worked at MIT Lincoln Laboratory since 2001 researching advanced microelectronics, semiconductor fabrication, embedded systems, and open and distributed architectures. He is currently on an IPA assignment to the Office of the Deputy Assistant Secretary of Defense for Systems Engineering (ODASD (SE)), where he serves as Deputy Director assigned to address near-term and longer term access to trusted and assured foundry capabilities.

Keynote 4: Connected Devices, AI, and Scale – Trends Driving Semiconductor Innovation
(Phoenix Restaurant / Chinatown, 07:00 - 9:30, Thursday, May 24)

Moderator: Deming Chen, University of Illinois at Urbana–Champaign
 
Abstract:
    Rapid adoption and production deployments of connected devices, coupled with AI-driven methods of advanced analytics, have led to an explosion in demand for non-traditional, more scalable computing and data management platforms. This increasing demand is being seen in the public cloud as well as in cloud-connected IoT edge devices. AI is at the heart of many the newest, most advanced analytics and IoT applications, ranging from robotics and autonomous vehicles, to cloud-connected products such as Amazon Alexa, to smart factories and consumer-facing services in the financial and healthcare sectors. This talk presents examples of such use-cases within Amazon, as well examples of how Amazon customers increasingly rely on AI coupled with IoT hardware and software stacks to innovate faster, and at cloud scales. The talk will conclude with examples of how cloud-based semiconductor design and manufacturing are being enhanced using these same methods.
 
Bio:
    Mr. David Pellerin serves as Head of Worldwide Business Development for Infotech/Semiconductor at Amazon Web Services. Prior to joining AWS, Mr. Pellerin had a career in electronic design automation and hardware-accelerated reconfigurable computing. He has experience with digital logic simulation and optimization, high-level synthesis, grid and cluster computing, FPGA design, and embedded systems. He has published five Prentice Hall technical books including “Practical Design Using Programmable Logic”, “VHDL Made Easy”, and “Practical FPGA Programming in C”.

Keynote 5: A Cross-Layer Perspective for Energy Efficient Processing - From beyond-CMOS devices to deep learning
(Water Tower AB - Floor 2, 9:00 - 10:00, Friday, May 25)

Moderator: Yanjing Li, University of Chicago
 
Abstract:
    As Moore’s Law based device scaling and accompanying performance scaling trends are slowing down, there is increasing interest in new technologies and computational models for fast and more energy-efficient information processing. Meanwhile, there is growing evidence that, with respect to traditional Boolean circuits and von Neumann processors, it will be challenging for beyond-CMOS devices to compete with the CMOS technology. Nevertheless, some beyond-CMOS devices demonstrate other unique characteristics such as ambipolarity, negative differential resistance, hysteresis, and oscillatory behavior. Exploiting such unique characteristics, especially in the context of alternative circuit and architectural paradigms, has the potential to offer orders of magnitude improvement in terms of power, performance and capability.
    In order to take full advantage of beyond-CMOS devices, however, it is no longer sufficient to develop algorithms, architectures and circuits independent of one another. Cross-layer efforts spanning from devices to circuits to architectures to algorithms are indispensable. This talk will examine energy-efficient neural network accelerators for embedded applications in this context. Several deep neural network accelerator designs based on cross-layer efforts spanning from alternative device technologies, circuit styles and architectures will be highlighted. A comprehensive application-level benchmarking study for the MNIST dataset will be presented. The discussions will demonstrate that cross-layer efforts indeed can lead to orders of magnitude gain towards achieving extreme scale energy-efficient processing.
 
Bio:
    Dr. X. Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, USA. Her research interests include low-power system design, circuit and architecture design with emerging technologies, hardware/software co-design and real-time embedded systems. She has published more than 300 papers in these areas. Some of her recognitions include the Best Paper Award from the Design Automation Conference and from the IEEE Symposium on Nanoscale Architectures, and the NSF CAREER award. She has participated in several large government and industry sponsored center-level projects and is a theme leader in an NSF/SRC E2CDA project. She is the General Chair of Design Automation Conference (DAC) in 2018, was the TPC chair of DAC in 2015, and was a member of TPC and Executive Committees of a number of other conferences. She also served as Associate Editor for IEEE Transactions on VLSI, ACM Transactions on Design Automation of Electronic Systems, etc. and is an Associate Editor of ACM Transactions on Cyber-Physical Systems. X. Sharon Hu is a Fellow of the IEEE.

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