Program Highlights
Keynotes
| Technical Sessions |
Special Sessions |
Poster Sessions |
Networking Events
You can download the FINAL
Program Schedule in PDF and check
every detail!
To all attendees:
There will be a cocktail
reception in the Alpine room on Tuesday, May 9th, between
19:00 - 20:30!
Keynotes
Cognitive Data-Centric Systems
Leland Chang
Senior Manager VLSI Design, IBM
Research
ABSTRACT
With rapid growth in the availability of massive amounts of data
and the development of new machine learning and deep learning techniques,
significant opportunities exist in the application of computing to learn from
data, build models, and discover insights - cognitive tasks that can augment
human expertise in a broad range of industries. Computing systems must evolve
to efficiently meet these needs by leveraging innovation in heterogeneous systems
infrastructure and information technology consumption models that are
increasingly driven by public and private cloud-based delivery. These new
systems must be designed to accommodate the entirety of the overall workflow,
including not just machine learning and analytics tasks, but also data
management and manipulation. In a convergence with systems for classical
modeling and simulation (HPC and technical computing), cognitive workloads can
benefit dramatically from hardware acceleration. As decades of sustained CMOS
technology scaling begins to slow, the specificity and optimality of hardware
accelerators will be a key enabler for system-level performance while
simultaneously presenting challenges in composing systems that seamlessly
integrate traditional CPUs, multiple accelerators, and different memories. This
talk will discuss cognitive data-centric systems for the next era of computing,
in which balanced heterogeneous systems are delivered through the cloud.
BIOGRAPHY
Leland Chang is the Senior Manager of VLSI Design at the IBM T. J.
Watson Research Center, where he leads a team driving the transition of new
research concepts into next-generation POWER server and System Z mainframe
products, including system architecture and microprocessor design implementation
as well as roadmap definition and applications analysis. With a technical
background spanning semiconductor technology, circuit design, system
architecture, and software algorithms, his key contributions have included the
FinFET structure for CMOS scaling, 8T-SRAM and high-speed register files for
embedded memory scaling, integrated voltage regulators with new passive device
technologies, and system design for emerging workloads such as machine learning
and deep learning. He received the B. S., M. S., and Ph.D. degrees in
electrical engineering and computer sciences from the University of California,
Berkeley, has authored more than 75 technical articles and 115 patents, and is
currently the memory subcommittee chair for the ISSCC technical program committee.
Internet-of-Medical-Things
Prof. Niraj K. Jha, Department of Electrical Engineering, Princeton University
jha@princeton.edu
ABSTRACT
We have arrived at the dawn of the
Internet-of-Things (IoT) era. 25 billion devices (things or physical objects)
are already connected to the Internet, and this number is expected to grow to
50 billion by 2020. IoT is a network of physical objects.These objects contain
sensors, actuators, and processing elements that enable us to gather data,
monitor the health of the object, make intelligent decisions, and optimize processes. IoT is expected to have a
potential economic impact of $3-6 trillion per year by 2025, with $1-2.5
trillion of this economic impact (its largest fraction) coming from smart healthcare
applications. These applications will be
enabled by a personal healthcare system consisting of implantable and wearable
medical sensors and devices connected to a personal health hub (e.g., a
smartphone or smartwatch) that is connected to the Internet.
In this talk, we will explore this
Internet-of-Medical-Things from two angles: energy-efficient inference and
security. We will first explore
energy-efficient inference on sensor nodes. This exploits sparsity, which is
characteristic of a signal that allows us to represent information efficiently.
We will look at an approach that enables efficient representations based on
sparsity to be utilized throughout a signal processing system, with the aim of
reducing the energy and/or resources required for computation, communication,
and storage. Such intelligent sensor nodes can be expected to be an important
building block of IoT. We will then show
how wearable medical sensors, which are being increasingly used as part of a
body-area network to provide proactive healthcare, can be used in a completely
different domain: continuous authentication, through monitoring of the
biological aura of the person. Unfortunately, as with any other technology,
along with the upside, we also have the downside of IoT - if the security
challenges facing IoT are not addressed, it may just become an
Internet-of-Things-to-be-Hacked. Hence, in the last part of the talk, we will
focus on the security of a body-area network that consists of implantable/wearable
medical devices and a health hub. We will
also explore physiological side channels that leak information about our health
condition.
BIOGRAPHY
Niraj K. Jha received his B.Tech. degree in
Electronics and Electrical Communication Engineering from Indian Institute of
Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering
from University of Illinois at Urbana-Champaign in 1985. He is a Professor of
Electrical Engineering at Princeton University. He has served as an Associate
Director for the Princeton Andlinger Center for Energy and the Environment. He
is a Fellow of IEEE and ACM. He has co-authored five books, among which are
"Switching and Finite Automata Theory, 3rd ed." and "Testing of Digital
Systems" that are textbooks being used around the world. He has served as the
editor-in-chief of IEEE Transactions on VLSI Systems and on the editorial
boards of several other IEEE Transactions. He is an author or co-author of more
than 430 papers among which are 14 award-winning papers. His research interests
include smart healthcare, machine learning, computer security, IoT,
energy-efficient design, IC design automation, FinFETs, and monolithic 3D IC
design.
FPGAs in the Datacenter -
Combining the Worlds of Hardware and Software
Development
Andrew Putnam
Microsoft
Research Technologies (MSR-T) lab
Andrew.Putnam@microsoft.com
ABSTRACT
The
Catapult project has brought the power and performance of FPGA-based
reconfigurable computing to Microsoft's hyperscale datacenters, accelerating
major production cloud applications such as Bing web search and Microsoft
Azure, and enabling a new generation of machine learning and artificial
intelligence applications. Catapult is now deployed in nearly every new server
across the more than a million machines that make up the Microsoft hyperscale
cloud.
The
presence of ubiquitous and programmable silicon in the datacenter ushers in a
new era where the discipline and rigor of the VLSI community are combining with
the speed and agility of the software community to form new opportunities in a
blend development styles and techniques.
In this talk, I will describe the next generation of the Catapult
configurable cloud architecture, and the tools and techniques that have made
Catapult successful to date. I will also discuss areas where traditional
hardware and software development flows fall short, and ways in which the VLSI
community can branch into new opportunities in software and computing.
BIOGRAPHY
Andrew Putnam is a Principal
Research Hardware Development Engineer in a collaboration between Microsoft
Azure and Microsoft Research NExT. He received a dual B.A/B.S. from the
University of San Diego in 2003, and an M.S. and Ph.D. in Computer Science and
Engineering from the University of Washington in 2006 and 2009 respectively.
His research focuses on reconfigurable computing, future datacenter design, and
computer architecture, with an emphasis on seeing research through from concept
to prototype to technology transfer. He was a founding member of the Microsoft
Catapult project, which was the first to put Field Programmable Gate Arrays
(FPGAs) into production hyperscale datacenters, doubling the capacity of each
server for web search, and creating the fastest network in the cloud.
Green Computing: New
Challenges and Opportunities
Alex K. Jones University of Pittsburgh
akjones@pitt.edu
ABSTRACT
As individuals and researchers approach the challenge
of green computing it is natural to consider the energy consumption of
computational devices and their supporting systems during their use phase
(i.e., after they are deployed into service). This includes reducing energy consumption in processors, memory systems,
peripheral devices, cooling systems and a host of other components that are
used in deployed systems. However, for
computing to be truly green, all phases of the system life-cycle, from
manufacturing to disposal, must be considered. In particular there is limited
awareness to the considerable fraction of the total life-cycle environmental
impacts of computing systems that result from the fabrication of the integrated
circuits (ICs) that are used in those devices. Studies have shown that the
energy and environmental costs of IC fabrication can actually significantly
outpace use-phase sustainability metrics and environmental impacts. With trends towards more exotic, thus, more
environmentally unfriendly, fabrication approaches at deeply scaled nodes,
life-cycle thinking for next generation computing systems that includes
traditional optimization of operational energy-efficiency as well as minimizing
impacts from IC fabrication is critical. In this talk I will present a new cadre of tools and methodologies to
holistically evaluate energy consumption and other environmental impacts from
computing. Based on these tools, I will
discuss new interdisciplinary research directions and educational opportunities
that emerge towards achieving more sustainable computing.
BIOGRAPHY
Professor Alex K Jones is a MCSI Faculty Fellow
in Sustainability and Director of Computer Engineering at the University of
Pittsburgh. In addition to sustainable
computing, his research interests include compilers, computer architectures,
electronic design automation, and reliability. He is the author of more than 140 publications in these areas. His research is funded by the U.S. National
Science Foundation, DARPA, CCC, the NSF CHREC center, and industry. Dr. Jones’ contributions have resulted in
several awards including an ACM/SIGDA Distinguished Service Award, a seminal paper
award from FCCM in addition to multiple best paper awards and nominations, a
University of Pittsburgh Innovator Award, and the 2017 Carnegie Science
Award. Recently, Dr. Jones led an effort
in visioning for the electronic design automation community funded by the
Computing Community Consortium (CCC). Dr. Jones is also actively involved in efforts to improve the scientific
method for experiments in computers science and engineering, to develop methods
reproducible research, and a centralized hub for computer architecture
simulators, emulators, benchmarks and experiments. He serves on many journal editorial boards
and conference committees including in area of sustainability, the IEEE
Transactions on Sustainable Computing and the IEEE International Green and
Sustainable Computing Conference. In his
spare time he performs as the principal clarinetist with the Pittsburgh
Philharmonic and Aeolian Winds and enjoys skiing and Tae Kwon Do.
Technical
Sessions
Wednesday, May 10, 2017
9:00 – 10:00
|
Keynote 1 - MT
Temple A
Leland Chang, Senior manager VLSI Design, IBM
Research
Cognitive Data-centric Systems
Moderator: Deming Chen, University of
Illinois at Urbana-Champaign, USA
|
10:00 – 10:20
|
Coffee Break - Trails Foyer
|
10:20 – 12:00
|
Session
1: Emerging Technologies and
Paradigms for Low Power Computing - Lakeshore
Session Chairs
Deliang Fan, University of Central Florida, USA (Chair)
Deming Chen, University of
Illinois at Urbana-Champaign, USA (Co-Chair)
1)
Design of a Low-Power Non-Volatile
Programmable Inverter Cell for COGRE-based Circuits, Fabrizio Lombardi, Pilin Junsangsri, Salin Junsangsri and Martin Margala
2)
VaLHALLA:
Variable Latency History Aware Local-carry Lazy Adder, Ali Murat Gok and Nikos Hardavellas
3)
Energy Efficient Magnetic Tunnel
Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device, Hao Cai, You Wang, Lirida Naviner, Wang Kang and Weisheng Zhao
4)
A
Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance, Xu He, Yao Wang, Yang Guo
and Sorin Cotofana
5)
*LightNN:
Filling the Gap between Conventional Deep Neural Networks and Binarized Networks (Best Paper Candidate), Ruizhou Ding, Zeye Liu,
Rongye Shi, Diana Marculescu
and Shawn Blanton
|
Session 2: Design Techniques for Non-Traditional Computing - Beehive
Session Chairs
Wujie Wen, Florida International University, USA (Chair)
Gang Qu, University of Maryland, USA (Co-Chair)
1)
Design of a Flash-based Circuit
for Multi-Valued Logic, Monther Abusultan and
Sunil Khatri
2)
Design of Approximate Logarithmic
Multipliers, Weiqiang
Liu, Jiahua Xu, Danye
Wang and Fabrizio Lombardi
3)
Mitigating the Effect of the Reliability
Soft-errors of the RRAM Devices on the Performance of the RRAM-based
Neuromorphic Systems, Amr Tosson, Shimeng Yu, Mohab Anis and Lan Wei
4)
A Spin Transfer Torque based Cellular
Neural Network (CNN) Architecture, Yu
Bai
5)
Neuro-NoC:
Neural Network based Predictive Routing for Network-on-Chip Architectures, Michel Kinsy and
Shreeya Khadka
|
12:00 – 1:30
|
Lunch
MT Temple A
|
1:30
– 2:50
|
Session 3: Strategies for
In-Memory Computing - Lakeshore
Session
Chairs
Jie Han, University of Alberta, Canada
(Chair)
Miroslav
Velev, Aries Design Automation, USA (Co-Chair)
1)
*A
Domain-Specific Language and Compiler for Computation-in-Memory Skeletons (Best Paper Candidate), Jintao
Yu, Tom Hogervorst and Razvan
Nane
2)
Energy Efficient In-Memory Computing
Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion
Devices, Shaahin Angizi, Zhezhi He and Deliang Fan
3)
Leveraging
Dual-Mode Magnetic Crossbar for Ultra-low Energy In-Memory Data Encryption, Zhezhi He, Shaahin Angizi, Farhana Parveen and Deliang Fan
4)
Evaluating Data Resilience in CNNs from
an Approximate Memory Perspective,
Yuanchang Chen, Yizhe
Zhu, Fei Qiao, Jie Han, Yuansheng Liu and Huazhong Yang
|
Special Session
1: Low Power
Computing based on Non-Volatile Memories - Beehive
Session
Chairs
Weisheng Zhao, Beihang
University
(Chair)
Damien
Querlioz, University of Paris Saclay,
CNRS (Co-Chair)
1)
Advanced
Low Power Spintronic Memories beyond STT-MRAM, Wang
Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang and Weisheng
Zhao
2)
Exploiting
Non-Volatility for Information Processing, Robert
Perricone, Li Tang, X. Sharon Hu and Michael Niemier
3)
Neuromorphic
Computing Based on Resistive RAM, Zixuan Chen, Huaqiang Wu, Bin Gao, Peng Yao, Xinyi Li and He Qian
4)
Implications
of the Use of Magnetic Tunnel Junctions as Synapses in Neuromorphic Systems, Adrien F. Vincent, Nicolas Locatelli, Qifan Wu and Damien Querlioz
5)
Bio-inspired
Programming of Resistive Memory Devices for Implementing Spiking Neural
Networks, Elisa Vianello,
Thilo Werner, Olivier Bichler,
Etienne Nowak, Alessandro Grossi, Blaise Yvert, Barbara De Salvo, and Luca Perniola
6)
|
2:50
– 3:50
|
Poster Session 1 - CAD, VLSI
Design, VLSI Circuits and Power Aware Design - MT Temple A
1)
A maze routing-based algorithm for ML-OARST with pre-selecting
and ripping up and re-building Steiner points, Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li and Rung-Bin Lin
2)
An Integrated Optimization Framework for Partitioning,
Scheduling and Floorplanning on Partially
Dynamically Reconfigurable FPGAs, Xiaodong Xu, Qi Xu, Jinglei Huang and Song Chen
3)
Communication-aware Partitioning for Energy Optimization of
Large FPGA Designs, Kalindu Herath, Alok Prakash, Jiang Guiyuan and
Thambipillai Srikanthan
4)
Combined Centralized and Distributed Connection Allocation in
Large TDM Circuit Switching NoCs, Yong Chen, Emil Matus
and Gerhard Fettweis
5)
Random Forest Architectures on FPGA for Multiple Applications, Xiang Lin, Shawn Blanton and Donald Thomas
6)
Exploring Heterogeneous-ISA Core Architectures for
High-Performance and Energy-Efficient Mobile SoCs, Wooseok Lee, Dam Sunwoo,
Christopher D. Emmons, Andreas Gerstlauer and Lizy John
7)
An FPGA Coarse Grained Intermediate Fabric for Regular
Expression Search, Thomas Luinaud, Pierre Langlois and Yvon Savaria
8)
Deadline-Aware Joint Optimization of Sleep Transistor and Supply
Voltage for FinFET Based Embedded Systems, Huimei Cheng, Ji Li, Jeffrey Draper, Shahin Nazarian and Yanzhi Wang
9)
Energy Savings and Performance Improvement in Subthreshold Using
Adaptive Body Bias, Rajsaktish Sankaranarayanan
and Matthew R. Guthaus
10) Low voltage stochastic flash ADC with front-end of
inverter-based comparative unit, Xuncheng Zou, Bo Liu
and Shigetoshi Nakatake
|
3:50
– 5:30
|
Session 4: Circuits, Architectures,
and System Level Issues for Many-Core Processors – Lakeshore
Session
Chairs:
Lombardi
Fabrizio, Northeastern
University, USA (Chair)
Ioannis
Savidis, Drexel University, USA (Co-Chair)
1)
*A
Robust C-element Design with Enhanced Metastability
Performance (Best Paper Candidate), Kinshuk Sharma and
Sunil Khatri
2)
Circuit
Level Design of a Hardware Hash Unit for use in Modern Microprocessors, Abbas Fairouz, Monther Abusultan and Sunil Khatri
3)
DELCA:
DVFS Efficient Low Cost Multicore Architecture, Shoumik Maiti and Sudeep Pasricha
4)
EEAL:
Processors' Performance Enhancement Through Early Execution of Aliased Loads,
Abhishek Rajgadia, Newton Singh and Virendra
Singh
5)
Performance-aware
resource management of multi-threaded applications on many-core systems, Daniel Olsen and
Iraklis Anagnostopoulos
|
Session 5: CAD for the Nano Era - Beehive
Session Chairs
Weichen Liu, Chongqing University, China (Chair)
Qiaoyan Yu, University of New Hampshire, USA
(Co-Chair)
1)
Redundant
Via Insertion with Cut Optimization for Self-Aligned Double Patterning, Youngsoo Song, Jinwook
Jung and Youngsoo Shin
2)
Improving
Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains, Zhufei Chu, Xifan
Tang, Mathias Soeken, Ana Petkovska,
Grace Zgheib, Luca Amaru,
Yinshui Xia, Paolo Ienne,
Giovanni De Micheli and Pierre-Emmanuel Gaillardon
3)
*Under-the-cell
Routing to Improve Manufacturability (Best Paper
Candidate), Àlex Vidal-Obiols,
Jordi Cortadella and Jordi Petit
4)
Boolean
Decomposition for AIG optimization, Lucas
Machado and Jordi Cortadella
5)
Mixed-Cell-Height
Standard Cell Placement Legalization, Chung-Yao
Hung, Peng-Yi Chou and Wai-Kei Mak
|
Thursday, May 11, 2017
9:00 – 10:00
|
Keynote 2 - MT Temple A
Professor Niraj K. Jha, Department of Electrical Engineering, Princeton
University
Internet of Medical Things,
Moderator: Jie Han, University of Alberta,
Canada
|
10:00 – 10:20
|
Coffee Break - Trails Foyer
|
10:20 – 12:00
|
Session 6: Hardware Security: New Advances in Timing Side Channel and Logic
Obfuscation - Lakeshore
Session Chairs
Houman Homayoun, George Mason University, USA (Chair)
Guru Venkataramani,
George Washington University, USA (Co-Chair)
1)
Covert
Timing Channels Exploiting Non-Uniform Memory Access based Architectures, Fan Yao, Guru Venkataramani
and Milos Doroslovacki
2)
A Novel
Side-channel Timing Attack on GPUs, Zhen Hang Jiang, Yunsi Fei and David Kaeli
3)
*A Low-Cost
Secure GPS Spoofing Detector Design for the Internet of Things Applications (Best Paper Candidate), Md Tanvir
Arafin, Dhananjay Anand and Gang Qu
4)
Cyclic Obfuscation for Creating
SAT-Unresolvable Circuits, Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan and Yier Jin
5)
Double DIP: Re-Evaluating Security of Logic
Encryption Algorithms, Yuanqi Shen and Hai Zhou
|
Session 7: Testing and Reliability- Beehive
Session Chairs
Chih-Tsun Huang, National Tsing Hua University, Taiwan (Chair)
Hung-Pin (Charles) Wen, National Chiao
Tung University, Taiwan (Co-Chair)
1)
*Efficient Critical Path
Selection Under a Probabilistic Delay Model (Best Paper Candidate), Ahish Mysore Somashekar
and Spyros Tragoudas
2)
Combining Restorability and Error Detection Ability for
Effective Trace Signal Selection, Binod Kumar, Ankit Jindal, Masahiro
Fujita and Virendra Singh
3)
Radiation-Hardened Designs for
Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops, Yuwen Lin, Charles H.-P. Wen, Herming Chiueh
4)
Effective Mitigation of Radiation-induced Single Event Transient
on Flash-based FPGAs, Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs and Raoul Grimoldi
5)
Energy Efficient Adaptive
Approach for Dependable Performance in the presence of Timing Interference, Nikolaos Zompakis,
Michail Noltsis, Dimitrios Rodopoulos, Francky Catthoor and Dimitrios Soudris
|
MS Session 1:
Plain of Six Glaciers
Moderator: Chris Miller, Rose-Hulman Institute of
Technology
1)
Design
Flows and Collateral for the ASAP7 7nm FinFET
Predictive Process Design Kit, Lawrence
Clark, Vinay Vashishtha, David Harris, Sam Dietrich
and Zunyan Wang
2)
WIP:
Open-Source Standard Cell Characterization Process-flow on 45 nm (FreePDK45),
0.18 μm, 0.25 μm,
0.35 μm and 0.5 μm,
Rabin Thapa,
Samira Ataei and James Stine
3)
SoC FPAA
Immersed Junior Level Circuits Course, Jennifer
Hasler, Aishwarya Aishwarya and Sahil Shah
4)
Teaching
Microelectronics at Olin College, Bradley
Minch
5)
Innovative
practice in the French microelectronics education targeting the industrial
needs, Olivier Bonnaud
and Laurent Fesquet.
|
12:00 – 1:30
|
Keynote
3 and Lunch - MT Temple A
Andrew Putnam, Microsoft Research Technologies
(MSR-T) lab
FPGAs in Datacenter – Combining the Worlds of
Hardware and Software Development,
Moderator: Miroslav Velev,
Aries Design Automation
|
1:30
– 2:50
|
Session 8: Emerging Technologies, RF Circuits and Security Functions - Lakeshore
Session Chairs
Tsung-Yi Ho, National Tsing Hua University,
Taiwan (Chair)
Deliang Fan, University of Central Florida, USA (Co-Chair)
1)
Design Automation for Paper
Microfluidics with Passive Flow Substrates , Joshua Potter, William Grover and Philip Brisk
2)
*Neuromorphic 3D Integrated
Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation
Computing (Best Paper Candidate), Md Amimul Ehsan, Zhen Zhou and Yang Yi
3)
Method
for Phase Noise Analysis of RF Circuits, Dimo Martev, Sven Hampel
and Ulf Schlichtmann
4)
Revealing
On-chip Proprietary Security Functions with Scan Side Channel Based Reverse
Engineering, Leonid
Azriel, Ran Ginosar and Avi Mendelson
|
Special Session 2: Three-Dimensional Integrated Circuit (3D-IC) Security - Beehive
Session Chair
Qiaoyan Yu, University of New Hampshire (Chair)
1)
Security Threats and Countermeasures in
Three-Dimensional Integrated Circuits , Jaya
Dofe, Peng Gu, Dylan
Stow, Qiaoyan Yu, Eren Kursun and Yuan Xie
2)
Impact of Power Distribution Network on
Power Analysis Attacks in Three-Dimensional Integrated Circuits, Jaya Dofe, Zhiming Zhang, Qiaoyan Yu, Chen
Yan and Emre Salman
3)
The Need for Declarative Properties in
Digital IC Security, Mohamed El Massad, Frank Imeson, Siddharth Garg and Mahesh Tripunitara
4)
Securing Split Manufactured ICs with
Wire Lifting Obfuscated Built-In Self-Authentication, Qihang Shi, Kan Xiao, Domenic Forte and Mark Tehranipoor
|
MS Session 2: Panel:
VLSI – The Tall Thin Designer Looks at 40: The Past, Present, and Future of
VLSI Design Education
- Plain of Six Glaciers
Moderator: John Nestor, Layfayette
College
Panelists:
David Harris, Harvey Mudd
College
Jennifer Hasler, Georgia
Tech
Russ Pina, MOSIS
James Stine, Oklahoma State University
This panel will explore the past, present, and future
of VLSI Design courses, reflecting on how the original courses impacted
education and technology, how courses have evolved over time in response to
changes in technology and design methods, and what we might expect in these
courses in the future.
|
2:50
– 3:20
|
Coffee Break - Trails Foyer
|
3:20
– 4:40
|
Special Session 3: Logic Obfuscation for IoT Security: A
New Arms Race? - Lakeshore
Yier Jin, University of Central
Florida (Chair)
Gang Qu, University of Maryland (Co-Chair)
1)
An Empirical Study on Gate Camouflaging
Methods Against Circuit Partition Attack, Xueyan Wang, Qiang Zhou, Yici
Cai and Gang Qu
2)
What to
Lock? Functional and Parametric Locking, Muhammad
Yasin, Abhrajit Sengupta, Benjamin Carrion Schafer, Yiorgos
Makris, Ozgur Sinanoglu and Jeyavijayan Rajendran
3)
Circuit Obfuscation and Oracle-guided
Attacks: Who Can Prevail?, Kaveh Shamsi, Meng Li, Travis Meade,
Zheng Zhao, David Z. Pan, and Yier Jin
4)
Comparative Analysis of Hardware
Obfuscation for IP Protection, Sarah
Amir, Bicky Shakya, Domenic
Forte, Mark Tehranipoor, and Swarup
Bhunia
|
Industry Academia Workshop – MT Temple A
Laleh Behjat, University of Calgary, Canada (Chair)
Tina Hudson, Rose-Hulman
University, USA (Co-Chair)
In this facilitated workshop, we will bring
together industry leaders, experienced faculty and students to discuss
industrial issues related to microelectronics education. At the beginning,
sponsoring companies will have an opportunity to present their university
relations programs and products in an interactive, small-group setting. Each
company will have a faculty advocate that uses their programs and/or
products. Participants will rotate to different companies through this part
of the workshop. In the second half of this workshop, small groups will have a
facilitated discussion about the changing role of education in preparing
students for the new challenges facing industry. Once the discussions are
over, there will be a sharing of the main ideas of each group on the themes.
The workshop will close by compiling a set of recommendations and best
practices.
|
5:00
– 7:00
|
Hike around
Lake Louise Shore line
Or
Chateau Lake
Louise Tour
|
7:00
– 9:00
|
Banquet, awards and Invited Talk – Victoria Ballroom
Invited
speaker: Dr. Eric Donovan, Professor and Associate Dean Research and Graduate Education
for the University of Calgary, Faculty of Science
S.T.E.V.E. - The Best
Backronym Ever!
Studying Aurora and the
role of citizen scientists
|
|
|
|
|
|
Friday, May 12, 2017
9:00 – 10:00
|
Keynote 4 - MT Temple A
Alex Jones, Professor, University of
Pittsburgh,
Green Computing: New Challenges and
Opportunities,
Moderator: Laleh Behjat, University of
Calgary, Canada
|
10:00 – 10:20
|
Coffee Break - Trails Foyer
|
10:20 – 12:00
|
Session 9: CAD under Challenges: Tight Constraints and
Unreliability - Lakeshore
Session Chairs
Jing-Jia Liou, National Tsing Hua University, Taiwan (Chair)
Wujie Wen, Florida International
University, USA (Co-Chair)
1)
Analysis of Single Event Upsets in
Combinational Designs at RTL Based on Satisfiability Modulo Theories, Ghaith Kazma, Ghaith Bany Hamad, Otmane Ait Mohamed and Yvon Savaria
2)
Fine-Grain Program Snippets Generator
for Mobile Core Design, Shuang Song, Raj Desikan, Mohamad Barakat, Sridhar
Sundaram, Andreas Gerstlauer
and Lizy K. John
3)
Coupling-Aware Functional Timing
Analysis for Tighter Bounds: How Much Margin Can We Relax?,
Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang and Charles H.-P. Wen
4)
Thermal Constrained Energy Efficient
Real-Time Scheduling on Multi-Core Platforms, Shi Sha, Wujie
Wen, Shaolei Ren and Gang Quan
5)
5) Quantitative Modeling of Thermo-Optic
Effects in Optical Networks-on-Chip, Weichen Liu,
Peng Wang, Mengquan Li, Yiyuan
Xie and Nan Guan
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Session
10: Memory Design from Circuits
to Architectures - Beehive
Session Chairs
Ioannis Savidis,
Drexel University, USA (Chair)
Selcuk Kose,
University of South Florida, USA (Co-Chair)
1)
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set
Time, Samira Ataei and James Stine
2)
Building a Fast and Power Efficient
Inductive Charge Pump System for 3D Stacked Phase Change Memories, Lei Jiang,
Sparsh Mittal and Wujie
Wen
3)
Design Space Exploration of TAGE Branch
Predictor with Ultra-Small RAM, Chaobing Zhou, Libo Huang, Zhisheng Li, Tan
Zhang and Qiang Dou
4)
A Power Efficient Architecture
with Optimized Parallel Memory Accessing for Feature Generation, Peng Ouyang,
Shouyi Yin, Chunxiao
Xing, Leibo Liu and Shaojun
Wei
5)
Design of
Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition, Fabrizio Lombardi, Linbin Chen,
Weiqiang Liu, Jie Han and
Paolo Montuschi
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MS Technical Session
2:
Plain of Six Glaciers
Moderator: Mohammed Moshirpour, University of Calgary
1)
Indiana
Bicentennial Torch Project: Trial by Fire, Todd Wild, Gabriel Martini, Noah Chesnut
and Mark Johnson
2)
Teaching
Assembly Programming for ARM-based Microcontrollers in a Professional
Development Kit, Weiying Zhu
3)
From
Microelectronics to Making: Incorporating Microelectronics in a First-Year
Introduction to Engineering Course, John
Nestor
4)
Integrating
Emerging Memory Technologies into Undergraduate Logic Design Course: The
Impact of Context Based Teaching, Arifa Hoque, William Sutton, Kawsher
Roxy and Sanjukta Bhanja
5)
SF3: A
Scalabe and Flexible FPGA-Framework for Education
and Rapid Prototyping, Jan Dürre and Holger Blume
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12:00 – 1:30
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Lunch and
Poster Session 2 - MT
Temple A
Testing/Reliability/Fault-Tolerance, Biochips
and Biological Systems, Emerging Computing & Post-CMOS Technologies,
Hardware Security
Moderator: Mark Johnson
1)
Throughput Optimization for Lifetime
Budgeting in Many Core Systems, Liang Wang, Xiaohang
Wang, Ho-Fung Leung and Terrence Mak
2)
A Test Pattern Quality Metric for
Diagnosis of Multiple Stuck-at and Transition faults, Sarmad
Tanwir, Michael Hsiao and Loganathan Lingappan
3)
Switched Capacitor and Infinite Impulse
Response Summation For A Quarter-Rate DFE With 4Gb/s Data Rate, Gyunam Jeon and Yong-Bin Kim
4)
Reducing Microfluidic Very Large Scale
Integration (mVLSI) Chip Area by Seam Carving, Brian
Crites, Karen Kong and Philip Brisk
5)
LUTOSAP: Lookup-Table-Based Online Sample
Preparation in Microfluidic Biochips, Lingxuan
Shao, Yibin Yang, Hailong
Yao and Tsung-Yi Ho
6)
ProACt: A
Processor for High Performance On-demand Approximate Computing, Arun Chandrasekharan, Daniel Grobe, and Rolf Drechsler
7)
Softmax
Regression Design for Stochastic Computing Based Deep Convolutional Neural
Networks, Zihao Yuan, Ji Li, Zhe
Li, Caiwen Ding, Ao Ren,
Bo Yuan, Qinru Qiu,
Jeffrey Draper and Yanzhi Wang
8)
Computing Polynomials with Positive
Coefficients using Stochastic Logic by Double-NAND Expansion, Sayed Ahmad Salehi, Yin Liu, Marc Riedel and Keshab
Parhi
9)
On the Role of Sequential Circuits in
Stochastic Computing, Pai-Shun Ting and John Hayes
10)
Circuit Techniques for Online Learning
of Memristive Synapses in CMOS-Memristor
Neuromorphic Systems, Sagarvarma Sayyaparaju, Gangotree Chakma, Sherif Amer and Garrett S. Rose
11)
Mitigating Control Flow Attacks in
Embedded Systems with Novel Built-in Secure Register Bank, Sean
Kramer, Zhiming Zhang, Jaya Dofe
and Qiaoyan Yu
12)
Using Security Invariant to Verify
Confidentiality in Hardware Design, Shuyu Kong, Yuanqi Shen and Hai Zhou
13)
Leveraging All-Spin Logic to Improve
Hardware Security, Qutaiba Alasad, Jiann Yuan and Deliang Fan
Poster
Session MSE:
1)
CloudV: A Cloud-Based Educational Digital Design Environment, Mohamed Shalan and Sherief Reda
2)
Work in Progress: MicroElectronics
Cloud Alliance. The design of new Open Educational Resources for an
Educational Cloud, Rosario Gil-Ortego, Manuel
Castro-Gil, Slavka Tzanova
and Etienne Sicard
3)
WIP: Optimization Algorithms: A Key
Component of EDA Education, Florin Balasa and Safaa Mohamed
4)
Using Babbage’s Difference Engine to
Introduce Computer Architecture, William Richard
5)
On-die Thermal Evaluation System, Suresh
Parameswaran and Boon Ang
6)
An Adaptive Senior Design Course with an
Emphasis on Undergraduate Course Curriculum, Vishwa
Teja Alaparthy and Selcuk Kose
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1:30 – 2:50
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Special Session 4: Efficient IoT Systems: The Power of Heterogeneous
Integration - Lakeshore
Selcuk Kose, University of South
Florida (Chair)
Ioannis Savidis, Drexel University
(Co-Chair)
1)
Efficient and Secure On-Chip
Reconfigurable Power Delivery for IoT Devices, Selcuk Kose
2)
Design Space Modeling and Simulation for
Physically Constrained 3D CPUs, Caleb Serafy, Zhiyuan Yang and Ankur Srivastava
3)
Automated Design of Stable Power
Delivery Systems for Heterogeneous IoT Systems, Inna Partin-Vaisband
4)
Work Load Scheduling For Multi Core
Systems With Under-Provisioned Power Delivery, Divya Pathak, Houman Homayoun
and Ioannis Savidis
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Session on Innovation I - Ideation and Entrepreneurship Mindset - Beehive
Laleh Behjat, University of Calgary (Chair)
Alex Bruton, Professor of Entrepreneurship, University of
Calgary
This highly interactive session will challenge your
thinking about what it means to be innovative and entrepreneurial, it will
inspire action, and it will provide you with a suite of highly practical
tools you can take back to your desk on Monday to lead change at the next
whiteboard or on the back of the next napkin you run into.
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Session on Innovation II - Fostering the Entrepreneurial Mindset
Using the KEEN Foundation 3Cs - Plain
of Six Glaciers
Tina Hudson, Rose-Hulman Institute of
Technology
The KEEN foundation believes that every engineer,
regardless of position, can benefit from an entrepreneurial mindset. In this
interactive workshop, we will describe entrepreneurial mindset learning, the
KEEN Foundation's framework for helping every student develop an
entrepreneurial mindset, and methods that help you encourage this mindset in
your classroom.
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2:50 – 3:20
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Coffee Break
– Heritage Hall
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3:20 – 5:30
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Innovation Challenge - MT Temple A
Embedded Systems IoT
Application
Tina Hudson, Rose-Hulman
University, USA (Chair)
Laleh Behjat, University of Calgary, Canada
(Co-Chair)
In the Innovation Challenge, you will get to use your
Curiosity to experiment in small teams with several sensors on a Cypress
Embedded Systems board, and then Integrate this knowledge to propose an
application using these sensors. You will defend the Value of your
application and the Feasibility of implementation. Each group will
present their proposal at the end of the session. Best proposals will win a
Cypress board to take home with them.
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Other Activities:
Industry Academia Workshop
3:20pm-4:40pm, Thursday, May 11, 2017
Beehive
Chair: Laleh Behjat, University
of Calgary, Canada
Co-chair: Tina Hudson, Rose-Hulman
University, USA
In this facilitated workshop,
we will bring together industry leaders, experienced faculty
and students to discuss industrial issues related to
microelectronics education. At the beginning, sponsoring
companies will have an opportunity to present their
university relations programs and products in an
interactive, small-group setting. Each company will have a
faculty advocate that uses their programs and/or products.
Participants will rotate to different companies through this
part of the workshop. In the second half of this workshop,
small groups will have a facilitated discussion about the
changing role of education in preparing students for the new
challenges facing industry. Once the discussions are over,
there will be a sharing of the main ideas of each group on
the themes. The workshop will close by compiling a set of
recommendations and best practices.
Invited Session on
Innovation
1:30pm-2:50pm, Friday, May 12, 2017
Beehive
Chair: Laleh Behjat, University
of Calgary, Canada
Co-chair: Tina Hudson, Rose-Hulman
University, USA
Innovation Exchange
3:20pm-5:30pm, Friday, May 12, 2017
MT Temple A
Chair: Tina Hudson, Rose-Hulman
University, USA
Co-chair: Laleh Behjat,
University of Calgary, Canada
In this hands one workshop
you will get a chance to practice what you have learned in
the previous workshops. Participants will practice
innovation while developing an embedded systems application
for the innovation challenge and will practice fostering
innovation among the groups. The Innovation Exchange will be
an Internet of Things embedded systems project. Participants
will be placed in small groups to design an application of
their choosing that maximizes feasibility and impact using a
small subset of on-board sensors on Cypress Semiconductor’s
CY8CKIT-042-BLE Pioneer Prototyping kit.
Banquet Invited Talk
Room: Victoria Ballroom, Thursday, 7pm.
Title: S.T.E.V.E. - The Best
Backronym Ever!
Subtitle: Discovering Auroral
Beads and citizen scientists
SPEAKER: Dr. Eric Donovan
Department of Physics and Astronomy,
University of Calgary
Bio: Eric
Donovan is Associate Dean Research and Graduate Education
for the University of Calgary Faculty of Science. He is also
a space physicist who studies the aurora. Over the past 20
years, he and his team have developed the world's most
extensive network of ground-based instruments for remote
sensing the aurora and associated phenomena. His data is
used, together with measurements from instruments on NASA,
Canadian Space Agency, and European Space Agency satellites,
to investigate the physical processes at work in the
Near-Earth space environment. His discoveries include
auroral "beads" that form right before magnetospheric
substorms, and, more recently, 'Steve'.
This site is maintained by:
GLSVLSI 2017 Webmaster
Theo Theocharides (ttheocharides@ucy.ac.cy),
University of Cyprus.
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