GLSVLSI 2014
Houston, Texas, USA
May 21-23 2014

LINKS
Home
Organizing Committee
Program Committee
Program Schedule
Venue and Houston Information
Conference Registration
Social Events
Hotel Information
Call for Papers [pdf]
Paper Submission - NEW
Past Conferences
Contact Us

NEWS

GLSVLSI 2014,Houston, Texas, USA

 

OTHER INFORMATION

Call For Papers
 


 
SPONSORS 


 
 

 
TECHNICAL SUPPORT
 

archiv1



 

 

Tentative Program Schedule

Wednesday | Thursday | Friday

  Tuesday, May 20, 2014
19:00 Welcome Reception
   
   
  Wednesday, May 21, 2014
  Session A Session B
8:30 Registration / Welcome 
9:00 Opening & Keynote  I
  Chair: Tong Zhang, Rensselaer Polytechnic Institute, USA
  Speaker:  Professor Keshab Parhi, University of Minnesota
  "VLSI Systems for Neurocomputing and Health Informatics"
10:30 Coffee Break
  Reliability, Resiliency, Robustness I CAD
Session Chair: Martin Margala Session Chair: Yan Luo
University of Massachussets, Lowell, USA Oracle Inc. USA
10:45 Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis Horizontal Benchmark Extension for Improved Assessment of Physical CAD Research
  1Matheus Moreira, 1Ricardo Guazzelli, 1Guilherme Heck and 2Ney L. V. Calazans Andrew B. Kahng, Hyein Lee and Jiajia Li
  1PUCRS, Brazil; 2FACIN-PUCRS, Brazil UCSD, USA
11:10 System-level Reliability Exploration Framework for Heterogeneous MPSoC OCV-Aware Top-Level Clock Tree Optimization
  1Zheng Wang, 1Chao Chen, 2Piyush Sharma and 1Anupam Chattopadhyay 1Tuck Boon Chan, 1Kwangsoo Han, 1Andrew B. Kahng, 2Jae-Gon Lee and 1Siddhartha Nath
  1RWTH-Aachen University, Germany; 2I.I.T. Patna, India 1UCSD, USA; 2Samsung Electronics Co., Ltd., USA
11:35 A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness Modeling of the Charging Behavior of Li-Ion Batteries based on Manufacturer's Data
  Rickard Ewetz, Anirudh Udupa, Cheng-Kok Koh and Ganesh Subbarayan Alessandro Sassone, Donghwa Shin, Alberto Bocca, Alberto Macii, Enrico Macii and Massimo Poncino
Purdue University, USA Politecnico di Torino, Italy
11:55 A Feasibility Study on Robust Programmable Delay Element Design based on Neuron-MOS Mechanism High Level Energy Modeling of Controller Logic in Data Caches
  Renyuan Zhang and Mineo Kaneko 1Preeti Ranjan Panda, 2Sourav Roy, 2Srikanth Chandrasekaran, 1Namita Sharma, 1Jasleen Kaur, 1Sarath Kumar Kandalam and 1Nagaraj N.
  Japan Advanced Institute of Science and Technology, Japan 1Indian Institute of Technology Delhi, India; 2Freescale Semiconductor India Pvt. Ltd., India
12:15 Lunch
  Best Paper Session
Session Chair: Alex K. Jones       University of Pittsburgh, USA
13:30 3D-SWIFT: A High-Performance 3D-Stacked Wide IO DRAM
  1Tao Zhang, 2Ke Chen, 3Guangyu Sun and 1Yuan Xie  
1Pennsylvania State University, USA; 2Oracle Corp., USA; 3Peking University, China
14:00 Minimum Implant Area-Aware Gate Sizing and Placement
Andrew B. Kahng and Hyein Lee  
UCSD, USA  
14:30 A Multi-stage Leakage Aware Resource Management technique for Reconfigurable Architectures
Nam Khanh Pham, Amit Kumar Singh, and Akash Kumar  
National University of Singapore, Singapore  
15:00 Coffee Break
15:15 Poster Session 1
Session Chair: Rung-Bin Lin     Yuan Ze University, Taiwan
  A Performance Enhancing Hybrid Locally Mesh Globally Star NoC Topology Energy-efficient Wireless Network-on-Chip Architecture with Log-Periodic On-Chip Antennas
  1Tuhin Subhra Das, 1Prasun Ghosal, 2Saraju Mohanty and 2Elias Kougianos 1Md Shahriar Shamim, 1Naseef Mansoor, 2Aman Samaiyar, 1Amlan Ganguly, 3Sujay Deb and 3Shobha Sunndar Ram
  1Bengal Engineering and Science University, Shibpu. 2University of North Texas, USA. 1Rochester Institute of Technology, USA. 2Delhi Technological University, India. 3Indraprastha Institute of Technology, India.
  VLSI Implementation of Linear MIMO Detection With Boosted Communications Performance Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory
  Dominik Auras, Rainer Leupers and Gerd Ascheid 1Michael Gautschi, 2Davide Rossi and 1,2Luca Benini
  RWTH Aachen University, Germany 1ETH Zuerich, Switzerland. 2University of Bologna, Italy.
  Energy Optimal Sizing of FinFET Standard Cells Operating in Multiple Voltage Regimes Using Adaptive Independent Gate Control Performance Modeling of Virtualized Custom Logic Computations
Yue Fu, Yanzhi Wang, Xue Lin, Shahin Nazarian and Massoud Pedram Michael Hall and Roger Chamberlain
University of Southern California, USA Washington University in St. Louis, USA.
  A Low Power High Resolution Digital PWM with Process and Temperature Calibrations for Digital Controlled DC-DC Converters Scheduling of PDE Setting and Timing Tests for Post-Silicon Skew Tuning with Timing Margin
Jing Lu and Yong-Bin Kim Mineo Kaneko
Northeastern University, USA Japan Advanced Institute of Science and Technology, Japan.
  WeDBless : Weighted Deflection Bufferless Router for Mesh NoCs An Area Efficient Low Power High Speed S-Box Implementation Using Power-Gated PLA
  1Simi Sleeba, 2John Jose and 1Mini M.G. Ho Joon Lee and Yong-Bin Kim
  1Model Engineering College, India. 2Rajagiri School of Engineering and Technology, Kochi, India. Northeastern University, USA.
  Trade-off between Energy and Quality of Service Through Dynamic Operand Truncation and Fusion FPGA Based Implementation of a Genetic Algorithm for ARMA Model Parameters Identification
Wenchao Qian, Robert Karam and Swarup Bhunia Hocine Merabti and Daniel Massicotte
Case Western Reserve University Université du Québec à Trois-Rivières, Canada.
A Novel Low-Power and In-place Split-Radix FFT Processor Highly Adaptive and Congestion-aware Routing for 3D NoCs
  Zhuo Qian and Martin Margala 1Manoj Kumar, 1Vijay Laxmi, 1Manoj Gaur, 2Masoud Daneshtalab, 3Seok-Bum Ko and 4Mark Zwolinski
  University of Massachusetts Lowell, USA 1Malaviya National Institute of Technology, Jaipur, India. 2University of Turku, Finland. 3University of Saskatchewan, Saskatoon, Canada. 4University of Southampton, UK.
H.264 8x8 INVERSE TRANSFORM ARCHITECTURE OPTIMIZATION  
  1Fabio Pereira, 1Altamiro Susin, 1Andre Borin, 2Alexsandro Bonatto and 1Marcelo Negreiros  
  1UFRGS, Brazil. 2IFRS, Brazil.  
  Energy Efficient Systems Design Methodology
Session Chair: Alberto Macii  Session Chair: Ke Chen
Politecnico di Torino, Italy Oracle Corporation
16:15 Adaptive Compressive Sensing for Low Power Wireless Sensors Squash: A Scalable Quantum Mapper Considering the Ancilla Sharing
  Adam Watkins, Venkata Naresh Mudhireddy, Haibo Wang and Spyros Tragoudas Mohammad Javad Dousti, Alireza Shafaei Bejestan and Massoud Pedram
Southern Illinois University,USA University of Southern California, USA
16:45 Regulator-Gating: Adaptive Management of On-Chip Voltage Regulators Design and Analysis of Robust and Wide Operating Low-Power Level-Shifter for Embedded Dynamic Random Access Memory
Selcuk Kose Kenneth Ramclam and Swaroop Ghosh
University of South Florida,USA University of South Florida, USA
17:15 Logic Block and Design Methodology for Via-Configurable Structured ASIC using Dual Supply Voltages A Study on the use of Parallel Wiring Techniques for Sub-20nm Designs
  Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu and Rung-Bin Lin 1Rickard Ewetz, 1Cheng-Kok Koh, 2Wen-Hao Liu, 2Ting-Chi Wang and 3Kai-Yuan Chao
  Yuan Ze University, Taiwan 1Purdue University, USA; 2National Tsing Hua University, Taiwan; 3Intel, USA
19:00 Gala Dinner
  Chair: Joseph Cavallaro, Rice University, USA
  Speaker:  Professor Gene Frantz, Rice University (formerly with Texas Instruments)
  "Create, then Innovate" 
     
   
  Thursday, May 22, 2014
  Session A Session B
9:00 Keynote II
  Chair: Joseph Cavallaro, Rice University, USA
  Speaker:  Professor Edgar Sanchez-Sinencio, Texas A&M University
  "Smart Nodes of Internet of Things (IoT): A Hardware Perspective View & Implementation"
10:00 Coffee Break
  Reliability, Resiliency, Robustness II Application Specific Designs
Session Chair - Dimin Niu Session Chair - Houman Homayoun
Samsung Research, USA George Mason University, USA
10:15 WriteSmoothing: Improving Lifetime of Non-volatile Caches Using Intra-set Wear-leveling A Hybrid Framework for Application Allocation and Scheduling in Multicore Systems with Energy Harvesting
  1Sparsh Mittal, 2Jeffrey Vetter and 1Dong Li Yi Xiang and Sudeep Pasricha
  1Oak Ridge National Laboratory, USA; 2ORNL and Georgia Tech, USA Colorado State University, USA
10:40 Reliability-Aware Cross-Point Resistive Memory Design Neural Network-Based Accelerators for Transcendental Function Approximation
  1Cong Xu, 1Dimin Niu, 1Yang Zheng, 2Shimeng Yu and 1Yuan Xie Schuyler Eldridge, Florian Raudies, David Zou and Ajay Joshi
  1Pennsylvania State University, USA; 2Arizona State University, USA Boston University, USA
11:05 Using adaptive read voltage thresholds to enhance the reliability of MLC NAND Flash memory systems Efficient Parallel Beamforming for 3D Ultrasound Imaging
  1Nikolaos Papandreou, 1Thomas Parnell, 1Haris Pozidis, 1Thomas Mittelholzer, 1Evangelos Eleftheriou, 2Charles Camp, 2Tom Griffin, 2Gary Tressler and 2Andrew Walls Pirmin Vogel, Andrea Bartolini and Luca Benini
  1IBM Research - Zurich, Switzerland; 2IBM Systems and Technology Group, USA ETH Zurich, Switzerland
11:25 A New Methodology for Reduced Cost of Resilience A task-oriented vision system
  Andrew Kahng, Seokhyeong Kang and Jiajia Li 1Yang Xiao, 2Chuanjun Zhang, 1Kevin Irick, 1Jack Sampson and 1Vijaykrishnan Narayanan
  UCSD, USA 1Pennsylvania State University, USA; 2Intel ISTC_EC, USA
11:45 Lunch
  Memory Designs Fault Tolerance
Session Chair: Nikolaos Papandreou  Session Chair: Ann Gordon-Ross 
IBM Research GmbH, Zurich Research Laboratory University of Florida, USA
13:00 A New DRAM Architecture and its Control Method for the System Power Consumption MB-FICA: Multi-bit Fault Injection and Coverage Analysis
Yoshiro Riho and Kazuo Nakazato Chen Jiang, Mojing Liu and Brett Meyer
Nagoya University, Japan McGill University, Canada
13:25 A Memory Mapping Approach based on Network Customization to Design Conflict-Free Parallel Hardware Architectures On-Line Detection of the Deadlocks Caused by Permanently Faulty Links in Quasi-Delay Insensitive Networks on Chip
Saeed Ur Rehman, Cyrille Chavet and Philippe Coussy   Wei Song, Guangda Zhang and Jim Garside
Universite de Bretagne-Sud / Lab-STICC, France University of Manchester, United Kingdom
13:50 New 4T-Based DRAM Cell Designs A novel parallel adaptation of an implicit path delay grading method
  1Fabrizio Lombardi, 1Wei Wei and 2Kazuteru Namba Joseph Lenox and Spyros Tragoudas
  1Northeastern University, USA; 2Chiba University, Japn SIU Carbondale, USA
14:15 Coffee Break
14:30 Poster Session 2
Session Chair: Prasun Ghosal    Indian Institute of Engineering Science and Technology, Shibpur, India
  Simscape Design Flow for Memristor Based Programmable Oscillators Built-In Generation of Functional Broadside Tests Considering Primary Input Constraints
  Ebubechukwu Agu, Saraju Mohanty, Elias Kougianos and Mahesh Gautam 1Bo Yao, 1Irith Pomeranz, 2Srikanth Venkataraman and 2Enamul Amyeen
  University of North Texas, USA. 1Purdue University, USA. 2Intel Corporation, USA.
Securely Outsourcing Power Grid Simulation on Cloud TSV Power Supply Array Electromigration Lifetime Analysis in 3D ICs
Naval Gupte and Jia Wang Qiaosha Zou, Tao Zhang and Yuan Xie
Illinois Institute of Technology, USA. Pennsylvania State University
  Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs A Current-Mode CMOS/Memristor Hybrid Implementation of an Extreme Learning Machine
Jin-Tai Yan Cory Merkel and Dhireesha Kudithipudi
Chung-Hua University, Taiwan. Rochester Institute of Technology, USA.
  An Automated Design Approach to Map Applications on CGRAs Modelling and Mitigation of Time-Zero Variability in sub-16nm FinFET-based STT-MRAM Memories
  1Thomas Peyret, 1Gwenolé Corre, 1Mathieu Thevenin, 2Kevin Martin and 2Philippe Coussy Matthias Hartmann, Halil Kukner, Prashant Agrawal, Praveen Raghavan, Liesbet Van Der Perre and Wim Dehaene
  1CEA, LIST, France. 2Université de Bretagne-Sud, France. IMEC VZW, KU Leuven, Belgium.
  He-P2012: architectural heterogeneity exploration on a scalable many-core platform A Design Flow for Physical Synthesis of Digital Cells with ASTRAN
  1Francesco Conti, 2Chuck Pilkington, 3Andrea Marongiu and 3Luca Benini 1Adriel Ziesemer Jr., 1Ricardo Reis, 2Matheus Moreira, 2Michel Arendt and 2Ney L. V. Calazans
  1University of Bologna, Italy. 2STMicroelectronics, Canada. 3University of Bologna & ETH Zurich, Italy. 1UFRGS, Brazil. 2PUCRS, Brazil.
  On Macro-Fault: A New Fault Model, Its Implications On Fault Tolerance And Manufacturing Yield A Semi-Formal Approach for Analog Circuits Behavioral Properties Verification
  1Tak-Kei Lam, 1Xing Wei, 2Wen-Ben Jone, 1Yi Diao and 1Yu-Liang Wu Ons Lahiouel, Henda Aridhi, Mohamed H. Zaki and Sofiene Tahar
  1The Chinese University of Hong Kong, Hong Kong. 2University of Cincinnati, USA. Concordia University, Canada.
Transient Analysis of Gate Inside Junctionless Transistor(GI-JLT)  
Pankaj Kumar, Sangeeta Singh and Pravin Kondekar  
Indian Institute of Information Technology Design & Management, India.  
  Reconfigurable Components System Level Optimization
Session Chair: Karthikeyan Lingasubramanian  Session Chair: Selcuk Kose
University of Alabama at Birmingham, USA University of South Florida, USA
15:30 Reconfigurable STT-NV LUT-based Functional Units to Improve Performance in General-Purpose Processors A Complete Electronic Network Interface Architecture for Global Contention-Free Communication over Emerging Optical Networks-on-Chip
  1Adarsh Reddy Ashammagari, 2Hamid Mahmoodi, 3Tinoosh Mohsenin and 1Houman Homayoun 1Marta Ortín Obón, 2Luca Ramini, 2Herve Tatanguem Fankem, 1Victor Vinals-Yufera and 2Davide Bertozzi
  1George Mason University, USA; 2San Francisco State University, USA; 3University of Maryland Baltimore County, USA 1University of Zaragoza, Spain; 2University of Ferrara, Italy
15:55 A Generic Implementation of a Quantified Predictor for FPGAs A Design Approach to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerator
  Gervin Thomas, Ahmed Elhossini and Ben Juurlink 1Mohamed Ben Hammouda, 2Philippe Coussy and 3Loic Lagadec
  Technical University of Berlin, Germany 1Universite de Bretagne Occidentale, France; 2Universite de Bretagne-SUD, France; 3ENSTA-Bretagne, France
16:20 A Dual-Rail LUT for Reconfigurable Logic using Null Convention Logic Thermal-aware Phase-based Tuning of Embedded Systems
Jing Yu and Paul Beckett Tosiron Adegbija and Ann Gordon-Ross
RMIT University, Australia University of Florida, USA
     
   
  Friday, May 23, 2014
  Session A Session B
9:00 Keynote III
  Chair: Hai (Helen) Li, University of Pittsburgh, USA
  Professor Alex Jones, University of Pittsburgh
  "EDA for Extreme Scale Systems: Design Abstractions, Metrics, and Benchmarks"
10:00 Coffee Break
  Reconfigurable Systems Analog Design
Session Chair: Xi Chen Session Chair: Saraju Mohanty
Qualcomm Inc. USA University of North Texas, USA
10:15 Hardware Trojan Attacks in FPGA Devices: Threat Analysis and Effective Countermeasures Generation of Reduced Analog Circuit Models using Transient Simulation Traces
  1Sanchita Mal-Sarkar and 2Swarup Bhunia 1Paul Winkler, 2Henda Aridhi, 2Mohamed Zaki and 2Sofiene Tahar
  1Cleveland State University, USA; 2Case Western Reserve University, USA 1Leipzigs University of Applied Sciences, Germany; 2Concordia University, Canada
10:40 Forward-scaling, serially equivalent parallelism for FPGA placement A Novel Mixed-Signal Self-Calibration Technique for Baseband Filters in Systems-on-Chip Mobile Transceivers
Christian Fobel, Gary Grewal and Deborah Stacey Yongsuk Choi and Yong-Bin Kim
University of Guelph, Canada Northeastern University, USA
11:05 A Parallel and Reconfigurable Architecture for Efficient OMP Compressive Sensing Reconstruction A Qualitative Simulation Approach for Verifying PLL Locking Property
  1Amey Kulkarni, 2Houman Homayoun and 1Tinoosh Mohsenin Ibtissem Seghaier, Henda Aridhi, Mohamed H. Zaki and Sofiène Tahar
  1University of Maryland, Baltimore County, USA; 2George Mason University, USA Concordia University, Canada
11:25 Break
  Low Power Design Emerging Technologies
Session Chair: Akash Kumar  Session Chair: Zhenyu Sun
National University of Singapore, Singapore Broadcomm Inc., USA
11:40 Optimal Power Switch Design Methodology for Ultra Dynamic Voltage Scaling with a Limited Number of Power Rails An Optically Reconfigurable Gate Array with an angle-multiplexed holographic memory
  Yanzhi Wang, Xue Lin and Massoud Pedram 1Retsu Moriwaki, 2Hikaru Maekawa, 2Akifumi Ogiwara and 1Minoru Watanabe
  University of Southern California, USA 1Shizuoka University, Japan; 2Kobe City College of Technology, Japan
12:00 Level Shifter Planning for Timing Constrained Multi-Voltage SoC Floorplanning Variability-Aware Design of Double Gate FinFET-based Current Mirrors
  Zhufei Chu, Yinshui Xia and Lunyao Wang 1Dhruva Ghai, 2Saraju Mohanty, 1Garima Thakral and 2Oghenekarho Okobiah
  Ningbo University, China 1Oriental University, India; 2University of North Texas, USA
12:20 Exploiting Heterogeneity in MPSoCs to Prevent Potential Trojan Propagation across Malicious IPs A Comparison of FinFET based FPGA LUT Designs
Chen Liu and Chengmo Yang Monther Abusultan and Sunil Khatri
University of Delaware, USA Texas A&M University, USA
12:40 Closing Session

 

 

 

 

 

 

 


 

This site is maintained by:
GLSVLSI 2014 Webmaster
Theo Theocharides (ttheocharides@ucy.ac.cy), University of Cyprus.