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| Welcome Reception (Bay Room): 6 pm - 9 pm, Tuesday, June 11 |
Keynotes
Keynote 1: Moore's Law, Advanced Packaging and Heterogeneous Integration
Do they hold the key for enabling Future Systems?
Dr. Madhavan Swaminathan
Department Head of Electrical Engineering & William E. Leonhard Endowed Chair
Director, Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES)
The Pennsylvania State University, USA
Abstract: Moore's law has helped us for 5+ decades through monolithic integration with packaging taking a back seat.
We have now reached a stage in the semiconductor industry where advanced packaging is beginning to take the front seat, with billions of dollars being invested in it.
Does this mean the end of Moore's law? So, what has changed for packaging to take center stage?
Is heterogeneous integration the same as what has been practiced in the past?
This talk will address several of these issues in the context of emerging applications and systems.
Bio: Madhavan Swaminathan is the Department Head of Electrical Engineering and is the William E. Leonhard Endowed Chair at Penn State University.
He also serves as the Director for the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), an SRC JUMP 2.0 Center www.chimes.psu.edu.
Prior to joining Penn State, he was the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT).
Prior to GT, he was with IBM working on packaging for supercomputers.
He is the author of 650+ refereed technical publications and holds 31 patents.
He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS).
He is a Fellow of IEEE, Fellow of the National Academy of Inventors (NAI), Fellow of Asia-Pacific Artificial Intelligence Association (AAIA), and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society.
He has been recognized through many awards with the most recent one being the 2024 IEEE Rao R. Tummala Electronics Packaging Award (technical field award) for contributions to semiconductor packaging and system integration technologies that improve the performance, efficiency, and capabilities of electronic systems.
He received his MS and PhD degrees in Electrical Engineering from Syracuse University.
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Keynote 2: From Large Language Models to Pervasive General Intelligence:
The Path Forward
Dr. Keshab Parhi
Dept. of Electrical & Computer Engineering
University of Minnesota, Minneapolis
Abstract: The unprecedented power of large language models holds promise for design of computing systems that can achieve general intelligence by demonstrating broad capabilities of intelligence, including reasoning, planning, and the ability to learn from experience, and with these capabilities at or above human-level (Bubeck et al., GPT-4 paper). However, the path forward is unsustainable with respect to energy efficiency, growth in data required to train models, and safety and security of the models. This is because the current artificial intelligence systems are trained using correlation. We argue that future pervasive general intelligence (PGI) systems will need to be trained using much less data by exploiting prospective learning, as opposed to retrospective. These PGI systems can learn collaboratively on a continual basis, and will be able to make prospective higher quality decisions across time and space. These systems will achieve many orders of magnitude energy efficiency compared to their current counterparts.
Bio: Keshab K. Parhi received the Ph.D. degree from the University of California, Berkeley, in 1988.
He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently the Erwin A. Kelen Chair in Electrical Engineering in the Department of Electrical and Computer Engineering. He has published over 700 papers, is the inventor of 36 patents, and has authored the textbook VLSI Digital Signal Processing Systems (John Wiley & Sons, 1999).
His current research addresses VLSI architecture design of machine learning systems, hardware security, and data-driven neuroscience.
Dr. Parhi is the recipient of numerous awards including the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2017 Mac Van Valkenburg award and the 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, and the 2004 F. E. Terman award from the American Society of Engineering Education.
He received the 2013 Distinguished Alumnus award from the IIT Kharagpur.
He has served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part-I during 2004 and 2005, and currently serves as the Editor-in-Chief of the IEEE Circuits and Systems Magazine.
He is a Fellow of IEEE, ACM, AIMBE, AAAS, and the National Academy of Inventors (NAI).
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Keynote 3: The Chiplet Revolution
Andreas Olofsson
Founder and CEO of Zero ASIC
Talk Date: June 13th, 2024
Abstract: The compounding effect of monolithic miniaturization on electronics has been nothing short of miraculous.
Fifty plus years of Moore's Law has resulted in a million fold improvement in computing cost and efficiency.
ow that physical device scaling is finally approaching hard atomic limits, the question is: Where will the next million fold computing efficiency improvement come from?
Extreme domain specific circuit specialization can provide the next 1,000 boost, but this path is currently blocked by the prohibitive cost and complexity of chip design.
Chiplets offer a compelling solution to reducing the cost and time of chip design by raising the level of abstraction to the die level.
In this talk, I will present my experience with chiplets over the last decade, review the current obstacles to chiplet based design, and propose some potential paths for the future.
Bio: Andreas Olofsson is the founder and CEO of Zero ASIC, a chiplet semiconductor startup reducing the barrier to ASICs.
From 2017 - 2020, Mr. Olofsson was a program manager at DARPA, where he managed 8 different US research programs in heterogeneous integration, EDA, design & verification, high performance computing, machine learning, and analog computing.
From 2008-2017, Mr. Olofsson founded and managed Adapteva, an ultra lean fabless semiconductor startup that led the industry in processing energy efficiency.
Prior to Adapteva he worked at Analog Devices for 10 years as a design manager and architect for advanced DSPs and mixed signal devices, developing products that shipped in over 100 million systems.
Mr. Olofsson received his Bachelor of Science in Physics and Electrical Engineering and Master of Science in Electrical Engineering from the University of Pennsylvania.
He is a senior member of IEEE and holds nine U.S. patents.
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Keynote 4: Spintronics Beyond Memory Operations
Dr. Sanjukta Bhanja
Professor
Executive Associate Dean
University of South Florida
Talk Date: June 13th, 2024
Abstract: This talk explores the multifaceted capabilities of spintronic memory systems, encompassing in-memory processing, security applications, and solving complex optimization problems.
These advancements can potentially reshape the computing landscape by providing more efficient, secure, and accessible computational solutions.
It will be structured into two key segments: The first part of the talk focuses on the concept of processing within the memory itself, utilizing racetrack technology.
This involves harnessing the signatures from multiple memory cells to perform computational tasks directly within the memory array.
This innovative approach streamlines the data processing pipeline and explores the computational capacity inherent in the memory hardware.
The second aspect addresses the intriguing concept of using dipolar coupling between memory elements for information processing and transfer.
By exploiting the interactions between memory elements, novel opportunities for performing computations and data transfer emerge.
This can lead to more efficient and versatile computing systems.
The presentation's second part delves into applying spintronic memory as physically unclonable functions (PUFs).
These PUFs can generate unique and unforgeable security primitives, bolstering hardware security.
This can enhance the security of various systems and applications, making them more resistant to unauthorized access or tampering.
Bio: Dr. Sanjukta Bhanja received a bachelor's degree in Electrical Engineering from Jadavpur University, Calcutta, and a Master's degree from the Indian Institute of Science, Bangalore.
She earned her Ph.D. in Computer Science and Engineering from the University of South Florida, Tampa.
She is currently a professor at the Department of Electrical Engineering at the University of South Florida.
Currently, Bhanja serves as Executive Associate Dean for the College of Engineering since FY'2021.
Sanjukta Bhanja's research spans VLSI, nano-electronics, and applied physics, with external sponsorship from the National Science Foundation and NASA.
She has graduated 12 Ph.D. graduates who've excelled in high-tech industries and advises four doctoral students.
Her creative works are published in top-tier peer-reviewed journals and conferences, including high-impact journals such as Nature Nanotechnology.
She has been an Associate Editor of the IEEE Transactions on VLSI Systems and ACM Journal on Emerging Technologies in Computing Systems.
Besides serving on various IEEE and ACM conferences' Technical Program Committees (TPC), she has assumed leadership roles in Conference organization and steering committees.
She organized a National Science Foundation-sponsored conference on "Field-coupled Nano-computing" that created a roadmap and evaluated research progress in Field-coupled computing.
Her accolades include the NSF CAREER Award, "Outstanding Faculty Research Achievement Award" from USF, Outstanding Undergraduate Teaching recognition, the F.E.F William Jones Outstanding Mentor Award, and certification as an Executive Leadership Fellow in the ELATES at Drexel® program for 2020-2021.
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Keynote 5: Quantum Topology and ISA Collaborative Optimizations for Reduced Noise NISQ Circuits
Dr. Alex Jones
Deputy Division Director
Electrical, Communications and Cyber Systems (ECCS)
Engineering Directorate, National Science Foundation
Abstract: The promise of quantum computation comes from the ability to entangle multiple qubits to solve complex computing problems.
Current quantum computer offerings, such as the superconducting-based quantum machines offered by IBM and Google, are strongly entrenched in the Noisy Intermediate Scale Quantum (NISQ) class of machines.
Unfortunately, the noise in these machines limits the size of quantum circuits that can be realized before noise channels overcome the work by the quantum circuit.
By working collaboratively between the quantum device design, quantum architecture, and quantum transpilation flow, it is possible to significantly decrease circuit depth and increase the problem size that can be computed in NISQ machines.
In this talk I will present our recent findings for topology and gate co-design using Transmon qubits with SNAIL couplers.
I will discuss methods for reducing two-qubit gate pulse lengths to provide greater control over quantum computations while also addressing the overhead of one-qubit gates.
Using a concept called parallel drive, I will show how one-qubit gates can sometimes be eliminated by driving two-qubit and one-qubit gates at the same time without creating substantial calibration problems.
I will also demonstrate a new transpilation approach called MIRAGE that takes advantage of mirror gates to improve circuit depth in the case of restricted radix topologies and for better decomposition in high-radix topologies.
Bio: Dr. Jones Full Professor (with tenure) of Electrical and Computer Engineering and Professor of Computer Science and Professor of Physics & Astronomy (by courtesy) at the University of Pittsburgh.
He is currently serving as the Deputy Division Director of the Electrical, Communications and Cyber Systems (ECCS) Division at the US NSF.
Previously he was a Program Director and Cluster Lead for the Computer Systems Research (CSR) Cluster at the NSF in the CISE Directorate.
At the conclusion of his rotation at NSF Dr. Jones will join Syracuse University as Department Chair of Electrical Engineering and Computer Science (EECS) and Klaus Schroder Endowed Chair Professor of Engineering and Computer Science.
Dr. Jones' research interests include compilation for configurable systems and architectures, scaled and emerging memory, reliability, fault tolerance, quantum computing, and sustainable computing. He is the author of more than 200 publications in these areas.
His research is funded by the NSF, DARPA, NSA, ARO, LPS, foundation grants, and industry.
He is the steering committee chair for the IEEE International Green and Sustainable Computing Conference, an associate editor for the IEEE Transactions on Computers and Sustainable Computing: Informatics and Systems Journal.
Dr. Jones is a Fellow of the IEEE.
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Keynote 6: From Substrate Independent AI to Substrate Utilization:
Hardware and Systems Approach for Next Generation AI and AGI
Dr. Eren Kurshan
AI Researcher and Technology Executive
Executive-in-Residence
Head of Research and Methodology
Princeton University
Abstract: Artificial Intelligence encounters three grand challenges:
The Energy Challenge, characterized by a troubling and unsustainable rise in training energy consumption; The Alignment Challenge, where jailbroken and misaligned AI pose significant safety and societal threats; and The AGI Challenge, involving the transition to Artificial General Intelligence, of fully integrated, coherently functioning modalities and higher level functions.
We argue that effectively tackling these challenges relies on system design and leveragingsubstrate capabilities.
To enhance energy efficiency, it is essential to leave the current restrictive view of AI as a software only solution and embrace fully integrated system design and novel hardware technologies, such as neuromorphic computing.
Addressingalignment challenges involves recognizing the pivotal role of system architecture in moral decision-making, echoing the human brain's reliance on signal comparators, feedback mechanisms, and control functions, without which it will be nearly impossible toachieve alignment.
System design also proves essential for advancing AGI solutions from multiple narrow AI models to integrated co-processing and high-level AGI functions.
Bio: Dr. Eren Kurshan is an AI researcher and technology executive focused on building AI systems for large-scale industrial use cases.
Kurshan received her Ph.D. in Computer Science from the University of California, Los Angeles, as well as a Master's in Computer Science and a Bachelor'sin Electrical Engineering.
She serves as an Executive-in-Residence at Princeton University and the Head of Research and Methodology.
Prior to these roles, she led a number of AI/ML and emerging technology programs at Columbia University, J.P. Morgan and IBMT.J. Watson Research Labs.
She was a Visiting Fellow at Princeton's Center for Information Technology Policy (2015-2016) and served as an Adjunct Professor at Columbia University since 2014.
Dr. Kurshan published over 80 peer reviewed technical publicationsand ~260 patents, with approximately 100 granted.
She has served as an associate editor of several IEEE and ACM journals and transactions including the IEEE Transactions on Emerging Technologies in Computing, IEEE Transactions on Computers, ACM Journal ofEmerging Technologies in Computing, ACM Transactions on Design Automation of Electronic Systems and the Journal of Low Power Electronics.
She was the recipient of 2 Best Technical Paper Awards from IEEE and ACM conferences, as well as top inventor and licensingawards from Bank of America and IBM.
She received 2 Outstanding Research and Corporate Accomplishment Awards from IBM for her work on system design and optimization and emerging technology development respectively.
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Technical Session 1A
Wednesday
June 12
10:10 - 11:10
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Technical Session 1A: VLSI Circuits and Design I
Chair: Sheng Wei (Asso. Prof.)
Co-DTC: Concentric Trench-Based Fully Integrated Capacitors for Heterogeneous Integration Platforms
Yousef Safari, Yushu Zhao, and Boris Vaisband
HMNTT: A Highly Efficient MDC-NTT Architecture for Privacy-preserving Applications
Changxu Liu, Danqing Tang, Jie Song, Hao Zhou, Shoumeng Yan, and Fan Yang
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver
Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, and Zhouhao Yang
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Technical Session 1B
Wednesday
June 12
10:10 - 11:10
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Technical Session 1B: Testing, Reliability, Fault-Tolerance
Chair: Hu He (Assoc. Prof.)
IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications
Yan Aibin, Chen Dong, Xing Guo, Jie Song, Jie Cui, Tianming Ni, Patrick Girard, and Xiaoqing Wen
PerFT-N: Low-overhead Permanent Fault-Tolerance Mechanism for Neural Processing Units
Haojie Jian, Chao Chen, Zheng Wang, and Pengfei Wu
DETECTive: Machine Learning-driven Automatic Test Pattern Prediction for Faults in Digital Circuits
Vincenzo Petrolo, Sourav Medya, Mariagrazia Graziano, and Debjit Pal
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Technical Session 1C
Wednesday
June 12
10:10 - 11:10
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Technical Session 1C: Emerging Computing & Post-CMOS Technologies I
Chair: Shaahin Angizi (Assi. Prof.), Dayane Reis (Assi. Prof.)
Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic
Seunggyu Lee, Wonjae Lee, and Youngsoo Shin
AltGraph: Redesigning Quantum Circuits Using Generative Graph Models for Efficient Optimization
Collin Beaudoin, Koustubh Phalak, and Swaroop Ghosh
CASH: Criticality-Aware Split Hybrid L1 Data Cache
Shruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, and Sandeep Chandran
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Technical Session 1D
Wednesday
June 12
10:10 - 11:10
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Technical Session 1D: VLSI for Machine Learning and Artificial Intelligence I
Chair: Sercan Aygun (Assi. Prof.)
A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers
Gian Singh and Sarma Vrudhula
ML-Fusion: Determining Memory Levels for Data Reuse Between DNN Layers
Zikang Zhou, Xuyang Duan, Kaiqi Chen, Yaqi Chen, and Jun Han
EDA-schema: A Graph Datamodel Schema and Open Dataset for Digital Design Automation
(Best Paper Candidate)
Pratik Shrestha, Alec Aversa, Saran Phatharodom, and Ioannis Savidis
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Technical Session 2A
Wednesday
June 12
11:20 - 12:20
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Technical Session 2A: VLSI Circuits and Design II
Chair: Tooraj Nikoubin (Prof.), Ujjwal Guin (Assi. Prof.)
SCRIPT: A Multiobjective Routing Framework for Securing Chiplet Systems against DoS Attacks
Ebadollah Taheri, Pooya Aghanoury, Sudeep Pasricha, Mahdi Nikdast, and Nader Sehatbakhsh
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus Cavalcante, Alessandro Vanelli-Coralli, and Luca Benini
GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure Silicon
Pratyush Nandi, Anubhav Mishra, and Madhav Rao
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Technical Session 2B
Wednesday
June 12
11:20 - 12:20
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Technical Session 2B: IoT and Smart Systems I
Chair: Mohammed Alawad (Assi. Prof.)
DroneBandit: Multi-Armed Contextual Bandits for Collaborative Edge-to-Cloud Inference in Resource-Constrained Nanodrones
(Best Paper Nominee)
Guillaume Chacun, Mehdi Akeddar, Thomas Rieder, Bruno Da Rocha Carvalho, and Marina Zapater
MARS: MAximizing throughput for MPPT-based self-sustaining LoRa Systems
Ruben Dominguez, Jose Baca, and Chen Pan
Efficient Exploration in Edge-Friendly Hyperdimensional Reinforcement Learning
Yang Ni, William Y. Chung, Samuel Cho, Zhuowen Zou, and Mohsen Imani
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Technical Session 2C
Wednesday
June 12
11:20 - 12:20
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Technical Session 2C: Emerging Computing & Post-CMOS Technologies II
Chair: Siting Liu (Assi. Prof.)
Q-Embroidery: A Study on Weaving Quantum Error Correction into the Fabric of Quantum Classifiers
Avimita Chatterjee, Debarshi Kundu, and Swaroop Ghosh
A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System
Wenhui Zhang, Xinkuang Geng, Qin Wang, Jie Han, and Honglan Jiang
Application of Quantum Tensor Networks for Protein Classification
(Best Paper Nominee)
Debarshi Kundu, Archisman Ghosh, Srinivasan Ekambaram, Jian Wang, Nikolay Dokholyan, and Swaroop Ghosh
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Technical Session 2D
Wednesday
June 12
11:20 - 12:20
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Technical Session 2D: VLSI for Machine Learning and Artificial Intelligence II
Chair: Maryam Parsa (Assi. Prof.)
Energy Efficient Multi-Modal Stress Detection System with Dynamic Adaptive Spiking Neurons
Phani Pavan Kambhampati, Ajay B S, and Madhav Rao
Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration
Wendi Sun, Wenhao Sun, Yifan Wang, Yi Kang, and Song Chen
Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow
Fabian Lesniak, Annina Gutermann, Tanja Harbaum, and Juergen Becker
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Technical Session 3A
Wednesday
June 12
3:00 - 4:20
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Technical Session 3A: Computer-Aided Design (CAD) I
Chair: Hao Zheng (Asso. Prof.)
Incremental SAT-based Exact Synthesis
(Best Paper Nominee)
Sunan Zou, Jiaxi Zhang, and Guojie Luo
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs
Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, and Evangeline F.Y. Young
Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning
Yuchao Liao, Tosiron Adegbija, Roman Lysecky, and Ravi Tandon
Scalable Flip-Flop Clustering Using Divide and Conquer For Capacitated K-Means
Andrew B. Kahng, Sayak Kundu, and Shreyas Thumathy
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Technical Session 3B
Wednesday
June 12
3:00 - 4:20
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Technical Session 3B: Hardware Security I
Chair: Ujjwal Guin (Asso. Prof.), Sunwoong Kim (Assi. Prof.)
Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks
Armin Darjani, Nima Kavand, and Akash Kumar
The Fuzz Odyssey: Navigating Uncharted Territories in Hardware Design Verification
Raghul Saravanan and Sai Manoj Pudukotai Dinakarrao
On Hardware Trojan Detection using Oracle-Guided Circuit Learning
(Best Paper Nominee)
Rajesh Kumar Datta, Guangwei Zhao, Dipali Deepak Jain, and Kaveh Shamsi
DM-TEE: Trusted Execution Environment for Disaggregated Memory
Ke Xia and Sheng Wei
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Technical Session 4A
Thursday
June 13
10:10 - 11:30
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Technical Session 4A: VLSI Circuits and Design III
Chair: Madhav Rao (Asso. Prof.), Sercan Aygun (Assi. Prof.)
VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks
(Best Paper Nominee)
Duo Yu, Ang Li, Qin Wang, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, and Zhigang Mao
TTNNM: Thermal- and Traffic-Aware Neural Network Mapping on 3D-NoC-based Accelerator
Xinyi Li, Wenjie Fan, Heng Zhang, Jinlun Ji, Tong Cheng, Shiping Li, Li Li, and Yuxiang Fu
An Embedded Multi-Layer Spiral Square Inductor for Integrated Power Delivery - Physical Design and Analytical Models
Rami Rasheedi and Inna Partin-Vaisband
On Advanced Methodologies for Microarchitecture Design Space Exploration
Tianji Liu, Qijing Wang, Lixin Liu, Fangzhou Wang, and Evangeline F.Y. Young
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Technical Session 4B
Thursday
June 13
10:10 - 11:30
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Technical Session 4B: Computer-Aided Design (CAD) II
Chair: Ioannis Savidis (Asso. Prof.), Ram Vemuri (Prof.)
A Multi-agent Generative Model for Collaborative Global Routing Refinement
Qijing Wang, Jinwei Liu, Martin D.F. Wong, and Evangeline F.Y. Young
A Hybrid ECO Detailed Placement Flow for Improved Reduction of Dynamic IR Drop
Andrew B. Kahng, Bodhisatta Pramanik, and Mingyu Woo
A Bounding Box-based Net Partitioning Method for Double-sided Routing
Fang-Yu Hsu, Tzu-Chuan Lin, Wai-Kei Mak and Ting-Chi Wang
An Electromigration-Aware Wire Sizing Methodology via Particle Swarm Optimization
Olympia Axelou, Kostas Kolomvatsos, George Floros, Nestor Evmorfopoulos, Georg Georgakos, and George Stamoulis
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Technical Session 4C
Thursday
June 13
10:10 - 11:30
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Technical Session 4C: Hardware Security II
Chair: Aydin Aysu (Assis. Prof.), Vishnuvardhan Iyer (Postdoc)
EPIC: Efficient and Proactive Instruction-level Cyberdefense
Preet Derasari and Guru Venkataramani
Boolean Domain Attack on Corrupt and Correct Based Logic Locking Techniques
Joseph Madera and Kyle Juretus
SSFuzz:Generating syntactic and semantic seeds for RISC-V processors
Shaoqian Jin, Yulin Li, Liwei Chen, and Gang Shi
Accelerating Homomorphic Comparison Operations for Thresholding with an Asymmetric Input Range
Sunwoong Kim and Wonhee Cho
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Technical Session 5A
Thursday
June 13
1:10 - 2:30
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Technical Session 5A: Computer-Aided Design (CAD) III
Chair: Debapriya Basu Roy (Assi. Prof)
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing
Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F.Y. Young, and Martin D.F. Wong
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Shan Shen, Dingcheng Yang, Yuyang Xie, Chunyan Pei, Bei Yu, and Wenjian Yu
Feature Fusion based Hotspot Detection with R-EfficientNet
Chun Wang, Yi Fang, and Sihai Zhang
PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing
Feng Guo, Jiawei Liu, Jianwang Zhai, Jingyu Jia, Kang Zhao, and Chuan Shi
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Technical Session 5B
Thursday
June 13
1:10 - 2:30
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Technical Session 5B: Hardware Security III
Chair: Kyle Juretus (Asso. Prof.), Sunwoong Kim (Assi. Prof.)
Using EM Side-Channels Near a Bluetooth Server Implementation to Monitor Bit-Level Leakages in BLE Communication Channels
Vishnuvardhan Iyer and Jacob Rezac
DTjRTL: A Configurable Framework for Automated Hardware Trojan Insertion at RTL
Ruochen Dai, Zhaoxiang Liu, Orlando Arias, Xiaolong Guo, and Tuba Yavuz
DyFORA: Dynamic Firmware Obfuscation and Remote Attestation using Hardware Signatures
Sajeed Mohammad and Farimah Farahmandi
Comprehensive Analysis of Consistency and Robustness of Machine Learning Models in Malware Detection
Sreenitha Kasarapu, Dipkamal Bhusal, Nidhi Rastogi, and Sai Manoj Pudukotai Dinakarrao
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Technical Session 6A
Friday
June 14
1:20 - 2:20
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Technical Session 6A: IoT and Smart Systems II
Chair: Ram Vemuri (Prof.)
Resource-Aware Saliency-Guided Differentiable Pruning for Deep Neural Networks
Uttej Kallakuri, Edward Humes, and Tinoosh Mohsenin
KDTree-SOM: Self-organizing Map based Anomaly Detection for Lightweight Autonomous Embedded Systems
Ping-Xiang Chen, Dongjoo Seo, Biswadip Maity, and Nikil Dutt
A Cryptographic Hardware Engineering Course based on FPGA and Security Analysis Equipment
Zhaojun Lu, Qidong Chen, Peng Xu, Jiliang Zhang, and Gang Qu
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Technical Session 6B
Friday
June 14
1:20 - 2:20
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Technical Session 6B: Emerging Computing & Post-CMOS Technologies III
Chair: Mst Shamim Ara Shawkat (Assi. Prof)
Feature-driven Approximate Computing for Wearable Health-Monitoring Systems
Nishanth Chennagouni, Mashrafi Kajol, Diliang Chen, Dongpeng Xu, and Qiaoyan Yu
Can Stochastic Computing Truly Tolerate Bit Flips?
Yutong Wang, Zhaojun Ni, and Siting Liu
Probabilistic Bayesian Neural Networks for Efficient Inference
Mohammed Alawad
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Technical Session 6C
Friday
June 14
1:20 - 2:20
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Technical Session 6C: VLSI for Machine Learning and Artificial Intelligence III
Chair: Maryam Parsa (Assi. Prof.), Mehdi Akeddar (ML Engineer)
NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions
Arash Fayyazi, Mahdi Nazemi, Arya Fayyazi, and Massoud Pedram
HSCONN: Hardware-Software Co-Optimization of Self-Attention Neural Networks for Large Language Models
Siqin Liu, Prakash Chand Kuve and Avinash Karanth
A Design of Remote FPGA Experimental Teaching System Supporting Single-Board Multi-User and Multi-Board Single-User for MOOCs
Zhixiong Di, Xufeng Wei, Yiduo Chen, Shuanglong Wu, Peihao Sun, and Qiang Wu
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Special Session 1
Wednesday
June 12
3:00 - 4:20
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Special Session 1: Hardware Implementation for Post-Quantum Cryptography and Homomorphic Encryption: Arithmetic, Architecture, and Security
Chair: Jiafeng Xie
LAMP: Efficient Implementation of Lightweight Accelerator for Polynomial MultiPlication, From Falcon to RBLWE-ENC
Pengzhou He, Ben Mongirdas, Cetin Koc, and Jiafeng Xie
Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMs
Prasanna Ravi, Shivam Bhasin, Anupam Chattopadhyay, Aikata Aikata, and Sujoy Sinha Roy
Exploring Generalization of Shoup Modular Multiplier
Oleg Mazonka, Mohammed Nabeel, and Michail Maniatakos
Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design
Suraj Mandal and Debapriya Basu Roy
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Special Session 2
Wednesday
June 12
3:00 - 4:20
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Special Session 2: Harnessing Large-scale Machine Learning Modules for Enhanced Design and Verification of Hardware Systems
Chair: Sai Manoj Pudukotai Dinakarrao
Assert-O: Context-based Assertion Optimization using LLMs
Samit Miftah, Amisha Srivastava, Hyunmin Kim, and Kanad Basu
Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive Analysis
Raghul Saravanan and Sai Manoj Pudukotai Dinakarrao
Harnessing Heterogeneity for Targeted Attacks on 3-D ICs
Alec Aversa and Ioannis Savidis
Navigating SoC Security Landscape on LLM-Guided Paths
Sudipta Paria, Aritra Dasgupta, and Swarup Bhunia
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Special Session 3
Thursday
June 13
1:10 - 2:30
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Special Session 3: Beyond Security of Silicon: Navigating the Hardware Security Landscape of Tomorrow
Chair: Hadi Mardani Kamali
Blockchain-Enabled Whitelisting Mechanisms for Enhancing Security in 3D ICs
Gaines Odom, Hardhik Mohanty, Ujjwal Guin, and Bhaskar Krishnamachari
SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation
Bulbul Ahmed, Sazadur Rahman, Kimia Zamiri Azar, Farimah Farahmandi, Fahim Rahman, and Mark Tehranipoor
Extended Abstract: Pre-Silicon Vulnerability Assessment for AI/ML Hardware
Furkan Aydin, Emre Karabulut, and Aydin Aysu
Evolutionary Large Language Models for Hardware Security: A Comparative Survey
Mohammad Akyash and Hadi Mardani Kamali
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Special Session 4
Friday
June 14
10:10 - 11:50
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Special Session 4: Low Power and Efficient Machine Learning: Moving Intelligence to the Edge
Chair: Avesta Sasan
Transductive Spiking Graph Neural Networks for Loihi
Shay Snyder, Victoria Clerico, Guojing Cong, Shruti Kulkarni, Catherine Schuman, Sumedh Risbud, and Maryam Parsa
Processing-in-Memory Designs Based on Emerging Technology for Efficient Machine Learning Acceleration
Bokyung Kim, Hai Li, and Yiran Chen
IRET: Incremental Resolution Enhancing Transformer
Banafsheh Saber Latibari, Soheil Salehi, Houman Homayoun, and Avesta Sasan
FFCL: Forward-Forward Net with Cortical Loops, Training and Inference on Edge Without Backpropogation
Ali Karkehabadi, Houman Homayoun, and Avesta Sasan
Energy Harvesting-assisted Ultra-Low-Power Processing-in-Memory Accelerator for ML Applications
Sanket Shukla, Sathwika Bavikadi, and Sai Manoj Pudukotai Dinakarrao
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Special Session 5
Friday
June 14
10:10 - 11:50
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Special Session 5: Next-generation Compute Acceleration with Emerging Circuits and Systems
Chair: Dharanidhar Dang
Fortified-Edge 4.0: A ML-Based Error Correction Framework for Secure Authentication in Collaborative Edge Computing
Seema Aarella, Venkata Prasanth Yanambaka, Saraju Mohanty, and Elias Kougianos
PositCL: Compact Continual Learning with Posit Aware Quantization
Vedant Karia, Abdullah Zyarah, and Dhireesha Kudithipudi
Ultra-Area-Efficient Cryogenic XNOR Logic Gate with Superconducting Heater Cryotron to Advance High-Performance Computing
Shamiul Alam and Ahmedullah Aziz
ToEFL: A Novel Approach for Training on Edge in Smart Agriculture
Alakananda Mitra, Saraju Mohanty, and Elias Kougianos
Designing Reconfigurable Interconnection Network of Heterogeneous Chiplets Using Kalman Filter
Siamak Biglari, Ruixiao Huang, Hui Zhao, and Saraju Mohanty
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Special Session 6
Friday
June 14
10:10 - 11:30
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Special Session 6: Security-by-Design for Smart Electronics
Chair: Venkata Prasanth Yanambaka
PACAC: PYNQ Accelerated Cardiac Arrhythmia Classifier with secure transmission - A Deep Learning based Approach
Soumyashree Mangaraj, Jaganath Prasad Mohanty, Samit Ari, Ayas Kanta Swain, and Kamalakanta
PUFshield: A Hardware-Assisted Approach for Deepfake Mitigation Through PUF-Based Facial Feature Attestation
Venkata Karthik Vishnu Vardhan Bathalapalli, Venkata Prasanth Yanambaka, Saraju Mohanty, and Elias Kougianos
Modular Security Evaluation Platform for Physiological Closed-Loop Control Systems
Samir Ahmed, Shakil Mahmud, and Robert Karam
Hardware Accelerated Quantized Hand Written DIGIT Recognition via High Level Synthesis
Pawan Oraon, Soumyashree Mangaraj, Ayas Kanta Swain, and Kamalakanta Mahapatra
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Invited Talk
Friday
June 14
11:30 - 11:50
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Invited Talk: Latest Advances in Post Quantum Cryptography
Reza Azarderakhsh
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Special Session 7
Friday
June 14
2:30 - 3:50
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Special Session 7: AI for Science at Hardware Platforms
Chair: Weiwen Jiang
Toward Fair Ultrasound Computing Tomography: Challenges, Solutions and Outlook
Yi Sheng, Junhuan Yang, Youzuo Lin, Weiwen Jiang, and Lei Yang
Enhanced AI for Science using Diffusion-based Generative AI - A Case Study on Ultrasound Computing Tomography
Junhuan Yang, Yi Sheng, Yuzhou Zhang, Hanchen Wang, Youzuo Lin, and Lei Yang
A Deep Multimodal Representation Learning Framework for Accurate Molecular Properties Prediction
Yuxin Yang, Zixu Wang, Pegah Ahadian, Abby Jerger, Jeremy Zucker, Song Feng, Feixiong Cheng, and Qiang Guan
Greener AI with Photonic Transformer-based Real-time Edge Intelligence
Dharanidhar Dang, Priyabrata Dash, and Ahmedullah Aziz
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Special Session 8
Friday
June 14
2:30 - 3:50
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Special Session 8: Signal Processing with Neuromorphic Computing
Chair: Shruti R. Kulkarni
Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing
Deniz Najafi, Sepehr Tabrizchi, Ranyang Zhou, Mohammadreza Amel Solouki, Andrew Marshall, Arman Roohi, and Shaahin Angizi
Asynchronous Neuromorphic Optimization in Lava
Shay Snyder, Sumedh Risbud, and Maryam Parsa
Event-Driven Sensing and Embedded Neuromorphic Platforms for Gamma Radiation Monitoring
Brett Witherspoon and Aaron Young
Review of Neuromorphic Processing for Vision Sensors
Mst Shamim Ara Shawkat, Shante Hicks, and Nahin Irfan
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Panel Session 1
Wednesday
June 12
1:50 - 2:50
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Panel Session 1: Next Generation Devices and System Integration
Moderator: Boris Vaisband - McGill University
Panelists: Madhavan Swaminathan - PSU, Keshab Parhi - UMN, Dayane Reis - USF, Anupam Chattopadhyay - NTU
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Panel Session 2
Thursday
June 13
2:40 - 3:40
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Panel Session 2: ML for Hardware Design and Hardware Design for ML
Moderator: Lu Peng - Tulane University
Panelists: Dimitrios Stamoulis - Microsoft, Andreas Olofsson - Zero ASIC, Qiaoyun Yu - UNH, Guru Prasadh Venkataramani - GWU, Alex Jones - NSF
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Poster Session 1
Wednesday
June 12
4:20 - 5:50
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Poster Session 1
Chair: Debjit Pal - UIC, Jie Gu - Northwestern University
VLSI Circuits and Design:
Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES)
Omid Bazgir, Satwik Gali, and Tooraj Nikoubin
A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations
Dhandeep Challagundla, Ignatius Bezzam, and Riadul Islam
Highly Efficient Load-Balanced Dataflow for SpGEMMs on Systolic Arrays
Guocheng Zhao, and Yongxiang Cao
A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation
Zihan Yin, Annewsha Datta, Shwetha Vijayakumar, Ajey Jacob, and Akhilesh Jaiswal
An Analytical Model for High-Frequency Through Silicon Vias
Mohamed Adel Gharib, Salma Abdelzaher, and Inna Partin-Vaisband
Generalizable and Relation Sensitive Netlist Representation for Analog Circuit Design
Surya Penmetsa, Fahad Rahman Amik, Zhanguang Zhang, Yingying Fu, Yingxue Zhang, Wulong Liu, and Jianye Hao
A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital Signature
Gaoming Du, Zhuo Chen, Zhenmin Li, Xiaolei Wang, and Duoli Zhang
Integrated MAC-based Systolic Arrays: Design and Performance Evaluation
Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G Gowda, and Madhav Rao
Improving Block Management in 3D NAND Flash SSDs with Sub-Block First Write Sequencing
Matchima Buddhanoy, Kamil Khan, Aleksandar Milenkovic, Sudeep Pasricha, and Biswajit Ray
Cost-Effective Value Predictor for ILP processors through Design Space Exploration
Ling Yang, Zhong Zheng, Libo Huang, Run Yan, Sheng Ma, Yongwen Wang, and Weixia Xu
Accelerating Boolean Constraint Propagation for Efficient SAT-Solving on FPGAs
Hariprasadh Govindasamy, Babak Esfandiari, and Paulo Garcia
IoT and Smart Systems:
FedTR: Federated Learning Framework with Transfer Learning for Industrial Visual Inspection
Vikash Sathiamoorthy, Shuo Huai, Hao Kong, Di Liu, Wendy Yong Yi Loy, Christian Makaya, Daren Ho, Ravi Subramaniam, Qian Lin, and Weichen Liu
Sparsifying Graph Neural Networks with Compressive Sensing
Mohammed Alawad
Advanced Continuous-Time Convolution Framework for Security Assurance in Wireless Sensor Networks
Mohammad Monjur and Qiaoyan Yu
Autotile: Autonomous Task-tiling for Deep Inference on Battery-less Embedded System
Jishnu Banerjee, Sahidul Islam, Wei Wei, Chen Pan, and Mimi Xie
Testing, Reliability, Fault-Tolerance:
Soft Error Resilience Analysis of LSTM Networks
Christopher P Vasquez, Travis LeCompte, Xu Yuan, Nianfeng Tzeng, and Lu Peng
Comprehensive Analysis of Generated Single Event Transients in Most Common Logic Cells of Skywater's 130 nm Technology
Janani Aravind and Daniel Limbrick
A Hardware Checkpoint-based Recovery Framework in Light Dual-core Lockstep Processors
Jingzhou Li, Huaiyu Chen, Wenbin Zhang, and Hu He
Microelectronic Systems Education:
Educational Tool-spaces for Convolutional Neural Network FPGA Design Space Exploration Using High-Level Synthesis
Richard C. Yarnell, Mousam Hossain, Raul Graterol, Ayush Pindoria, Sujan Ghimire, Muhtasim Alam Chowdhury, Soheil Salehi, Yu Bai, and Ronald F. DeMara
Step-by-Step Tutoring Support for Student Success in Circuit Analysis Courses
Brian Skromme, Megan O'Donnell, and Wendy Barnard
Late Breaking Results:
System Architecture Optimization for Vertical Power Delivery
Sriharini Krishnakumar, Yaroslav Popryho, and Inna Partin-Vaisband
GeckOpt: LLM System Efficiency via Intent-Based Tool Selection
Michael Fore, Simranjit Singh, and Dimitrios Stamoulis
Word2HyperVec: From Word Embeddings to Hypervectors for Hyperdimensional Computing
Alaaddin Goktug Ayar, Sercan Aygun, M. Hassan Najafi, and Martin Margala
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Poster Session 2
Thursday
June 13
3:50 - 5:20
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Poster Session 2
Chair: Debjit Pal - UIC, Jie Gu - Northwestern University
Computer-Aided Design:
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification
Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, and Rolf Drechsler
Anomaly Detection Method based on Discrete Particle Swarm Optimization for Continuous-Flow Microfluidic Biochips
Yangjie Wu, Yuhan Zhu, Genggeng Liu, Xing Huan
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation
Qijing Wang, Xiaopeng Zhang, Martin D.F. Wong, and Evangeline F.Y. Young
IR drop Prediction Based on Machine Learning and Pattern Reduction
Yong-Fong Chang, Yung-Chih Chen, Yu-Chen Cheng, Shu-Hong Lin, Che-Hsu Lin, Chun-Yuan Chen, Yu-Hsuan Chen, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Shih-Chieh Chang, Yi-Ting Li, and Chun-Yao Wang
An Automatic Insertion Scheme of Extra Via for DSA-MP Hybrid Lithography
Yuqin Wang, Cheng Guo, Xiaojing Su, Xin Hong, Zixi Liu, Xiaohuan Ling, Bojie Ma, Pengyu Ren, Yujie Jiang, Yajuan Su, and Yayi Wei
A P&R Co- Optimization Engine for Reducing Congestion
Dongliang Xia, Wenxin Yu, Chaoqi Fu, Zejun Gan, Chengjin Li, and Yupeng Zhang
Washing Optimization Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips
Junqian Huang, Yuhan Zhu, Xing Huang, and Genggeng Liu
Error Recovery Method Based on Deep Reinforcement Learning for Fully Programmable Valve Array Biochips
Zhenyuan Wu, Yuhan Zhu, Xing Huang, and Genggeng Liu
MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators
Jinyu Bai, He Zhang, Longchao Liu, Pengfei Li, and Wang Kang
Emerging Computing & Post-CMOS Technologies:
AFeCAM: An Energy Efficient Analog 1FeFET Content Addressable Memory
Sabrina Hassan Moon and Dayane Reis
A New Routing Strategy to Improve Success Rates of Quantum Computers
Fang Qi, Xin Fu, Xu Yuan, Nian-Feng Tzeng, and Lu Peng
RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security
Sepehr Tabrizchi, Nedasadat Taheri, Shaahin Angizi, and Arman Roohi
Evaluating Efficacy of Model Stealing Attacks and Defenses on Quantum Neural Networks
Satwik Kundu, Debarshi Kundu, and Swaroop Ghosh
Hardware Security:
SNAC: Mitigation of Snoop-Based Attacks with Multi-Tier Security in NoC Architectures
Siqin Liu, Saumya Chauhan, and Avinash Karanth
Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack
Tasnuva Farheen, Sourav Roy, Andrew Cannon, Jia Di, Shahin Tajik, and Domenic Forte
Detecting Hardware Trojans using Model Guided Symbolic Execution
Ruochen Dai and Tuba Yavuz
Breaching the Gap: Modelling SRAM-PUFs via Side-Channel Signatures
Kuheli Pratihar, Soumi Chatterjee, Rajat Subhra Chakraborty, and Debdeep Mukhopadhyay
Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion Ability
Gwok-Waa Wan, Sam-Zaa Wong, and Xi Wang
LDL-SCA: Linearized Deep Learning Side-Channel Attack Targeting Multi-tenant FPGAs
Yankun Zhu, Siting Liu, Liyu Yang, and Pingqiang Zhou
LISA: A Multi-Layered Iterative Framework for Hardening Obfuscation with Modular Unit Transformations
Rasheed Almawzan, Atri Chatterjee, Aritra Dasgupta, and Swarup Bhunia
VLSI for Machine Learning and Artificial Intelligence:
Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage
Zixi Liu, Yibo Lin, Xiaojing Su, Xiaohuan Ling, Xin Hong, Bojie Ma, Yajuan Su, and Yayi Wei
Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention Fusion
Yunji Qin, Wenqi Lou, Chao Wang, Lei Gong, and Xuehai Zhou
Performance Analysis of OFA-NAS ResNet Topologies Across Diverse Hardware Compute Units
Prashanth H C and Madhav Rao
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