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GLSVLSI 2020

Beijing, China, September 8-11, 2020 (Virtual)

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Advance Program

 
 
September 8 (Tuesday) September 9 (Wednesday)
8:00 a.m. (EDT)
-
9:00 a.m. (EDT)
 
Tech session 3A: 3D Flash Memory and FPGA Designs
Special session 3B: Efficient and Secure Deep Learning and Reinforcement Learning in Embedded Systems
8:30 - 9:00
Openning Session
9:00 a.m. (EDT)
-
09:45 a.m. (EDT)
Keynote 1:
Keynote 2: 
09:45 a.m. (EDT)
-
10:00 a.m. (EDT)
Break
Break
10:00 a.m. (EDT)
-
11:00 a.m. (EDT)
Tech session 1A: Machine Learning and Neuromorphic Accelerator Designs
Special session 1B: Emerging Memory-Enabled Computing for Future Electronics
Tech session 4A: Emerging Computing Circuits, Architectures, and Paradigms
Special session 4B: Advances in Microarchitecture Security: from Detection of Threats to Mitigation
11:00 a.m. (EDT)
-
12:00 p.m. (EDT)
Tech session 2A: Hardware Security and Testing
Special session 2B: In-Memory Computing for Advanced Machine Learning Applications: An EDA Perspective
Tech session 5A: Neural Network Acceleration and Approximate Computing
Special session 5B: Protecting the Hardware in the Manufacturing Supply Chain: A Special Session on Hardware Security
 
 
 
September 10 (Thursday) September 11 (Friday)
8:00 a.m. (EDT)
-
9:00 a.m. (EDT)
Tech session 6A: Network-on-Chip Designs and On-Chip Communication
Special session 6B: When Energy Efficiency and Multi-level Interaction Work Together
Poster session 1
Poster session 2
9:00 a.m. (EDT)
-
09:45 a.m. (EDT)
Keynote 3:
Keynote 4: 
09:45 a.m. (EDT)
-
10:00 a.m. (EDT)
Break
Best Paper Announcement
10:00 a.m. (EDT)
-
11:00 a.m. (EDT)
Tech session 7A: Machine-learning based Design Automation
Special session 7B: Security in/for Approximate Computing
Tech session 9A: 3D Circuits and Power Circuits
Panel_Sessions 2: Security and Privacy Issues in AI and Their Impacts on Hardware Security
11:00 a.m. (EDT)
-
12:00 p.m. (EDT)
Tech session 8A: Emerging Deep Neural Network Computing and In-Memory Computing Systems
Panel_Sessions 1: Cross-Layer Design of Cyber-Physical Systems: from Circuit to Cloud
Tech session 10A: Microelectronic Systems Education Workshop
Time to GLSVLSI2020:
 

Keynote 1: Deep Learning Processors for On-Device Intelligence

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Hoi-Jun Yoo, KAIST, Korea

Moderator: Weisheng Zhao, Beihang University
 
Abstract:
Bio:


Keynote 2: Towards Self-Aware Systems-on-Chip Through Intelligent Cross-Layer Coordination

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Fadi Kurdahi, UC Irvine, US

Moderator: Tinoosh Mohsenin, UMBC
 
Abstract:
Bio:


Keynote 3: Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices

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Deming Chen, UIUC, US

Moderator: Weisheng Zhao, Beihang University
 
Abstract:
Bio:


Keynote 4: Securing Machine Learning Architectures and Systems

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Nael Abu-Ghazaleh, UC Riverside, US

Moderator: Tinoosh Mohsenin, UMBC
 
Abstract:
Bio:


Technical Session 1A

Tuesday
September 8
 
10:00 - 11:00
Tech session 1A: Machine Learning and Neuromorphic Accelerator Designs
Chair: Tao Liu
 
SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform
(Best Paper Award Candidate)
Shimin Li, Shasha Guo, Limeng Zhang, Ziyang Kang, Shiying Wang, Wei Shi, Lei Wang and Weixia Xu
 
SIP: Boosting Up Graph Computing by Separating the Irregular Property Data
Jiacheng Ni, Xiaochen Guo and Yuanqing Cheng
 
On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation
Hongjie Xu, Jun Shiomi and Hidetoshi Onodera
 
BPhoton-CNN: An Ultrafast Photonic Backpropagation Accelerator for Deep Learning
Dharanidhar Dang, Aurosmita Khansama and Debashis Sahoo

Technical Session 2A

Tuesday
September 8
 
11:00 - 12:00
Tech session 2A: Hardware Security and Testing
Chair: Inna Partin Vaisband
 
Towards Programmable All-Digital True Random Number Generators
(Best Paper Award Candidate)
Rashmi Agrawal, Lake Bu, Eliakin del Rosario and Michel Kinsy
 
Boosting Entropy Extraction of PDL-based RO PUF by High-order Difference Method
Liang Zheng, Changting Li, Zongbin Liu and Cunqing Ma
 
A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM
Zhengyi Hou, You Wang, Deming Zhang, Hao Cai and Chengzhi Wang
 
Reliability-Enhanced Circuit Design Flow Based on Approximate Logic Synthesis
Zuodong Zhang, Runsheng Wang, Zhe Zhang, Chang Meng, Zhuangzhuang Zhou, Weikang Qian and Ru Huang

Technical Session 3A

Wednesday
September 9
 
08:00 - 09:00
Tech session 3A: 3D Flash Memory and FPGA Designs
Chair: Arman Roohi
 
Exploiting Disturbance-Aware Read Redirection for Performance Improvement in 3D Flash Memory
(Best Paper Award Candidate)
Jinhua Cui, Weiguang Liu, Jianhang Huang and Laurence T. Yang
 
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes
Vladimir Herdt, Daniel Grosse, Jonas Wloka, Tim Güneysu and Rolf Drechsler
 
MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique
Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu and Wenzhong Guo
 
A Tile-based Interconnect Model for FPGA Architecture Exploration
Chengyu Hu, Peng Lu, Wei Liu, Jian Wang and Jinmei Lai

Technical Session 4A

Wednesday
September 9
 
10:00 - 11:00
Tech session 4A: Emerging Computing Circuits, Architectures, and Paradigms
Chair: Bing Li
 
An Approximate Carry Estimating Simultaneous Adder with Rectification
(Best Paper Award Candidate)
Rajat Bhattacharjya, Vishesh Mishra, Saurabh Singh, Kaustav Goswami and Dip Sankar Banerjee
 
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits
Rongliang Fu, Zhi-Min Zhang, Guang-Ming Tang, Junying Huang, Xiao-Chun Ye, Dong-Rui Fan and Ning-Hui Sun
 
SIMDive: Approximate SIMD Soft Multiplier-Divider for FPGAs with Tunable Accuracy
Zahra Ebrahimi Mamaghani, Salim Ullah and Akash Kumar
 
Accelerating Deterministic Stochastic Computing with Context-Aware Bit-stream Generator
Sina Asadi and M. Hassan Najafi

Technical Session 5A

Wednesday
September 9
 
11:00 - 12:00
Tech session 5A: Neural Network Acceleration and Approximate Computing
Chair: Yu Bai
 
Fast ECO Leakage Optimization Using Graph Convolutional Network
(Best Paper Award Candidate)
Wonjae Lee, Yonghwi Kwon and Youngsoo Shin
 
An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN
Bo Liu, Yuhao Sun, Hao Cai, Zeyu Shen, Yu Gong, Lepeng Huang and Zhen Wang
 
TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries
Sheng Xu, Xiaoming Chen, Xuehai Qian and Yinhe Han
 
Power-Efficient Approximate Multiplier Using Adaptive Error Compensation
Zhixi Yang, Honglan Jiang, Xianbin Li and Jun Yang

Technical Session 6A

Thursday
September 10
 
08:00 - 09:00
Tech session 6A: Network-on-Chip Designs and On-Chip Communication
Chair: Riadul Islam
 
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip
(Best Paper Award Candidate)
Febin Sunny, Asif Mirza, Ishan Thakkar, Sudeep Pasricha and Mahdi Nikdast
 
Energy-Efficient On-Chip Networks through Profiled Hybrid Switching
Yuan He, Jinyu Jiao, Thang Cao and Masaaki Kondo
 
Redesigning Photonic Interconnects with Silicon-on-Sapphire Device Platform for Ultra-Low-Energy On-Chip Communication
Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai and Ishan Thakkar
 
COCOA: Content-Oriented Configurable Architecture based on Highly-Adaptive Data Transmission Networks
Tian Xia, Pengchen Zong, Haoran Zhao, Jianming Tong, Wenzhe Zhao, Nanning Zheng and Pengju Ren

Technical Session 7A

Thursday
September 10
 
10:00 - 11:00
Tech session 7A: Machine-learning based Design Automation
Chair: Xiaoqing Xu
 
ESNreram: An Energy-Efficient Sparse Neural Network Based on Resistive Random-Access Memory
Zhuoran Song, Yilong Zhao, Yanan Sun, Xiaoyao Liang and Li Jiang
 
Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning
Niklas Bruns, Daniel Grosse and Rolf Drechsler
 
Synthesizing Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems
Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen and Yi Kang
 
A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design
Peng Cao and Wei Bao

Technical Session 8A

Thursday
September 10
 
11:00 - 12:00
Tech session 8A: Emering Deep Neural Network Computing and In-Memory Computing Systems
Chair: Bonan Yan
 
Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead
Baogang Zhang, Necati Uysal, Deliang Fan and Rickard Ewetz
 
Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration
Zihan Zhang, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao and Naifeng Jing
 
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM
Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang and Weisheng Zhao
 
An Order Sampling Processing-in-Memory Architecture for Approximate Graph Pattern Mining
Ziqian Wan, Guohao Dai, Yun Joon Soh, Jishen Zhao and Yu Wang

Technical Session 9A

Friday
September 11
 
10:00 - 11:00
Tech session 9A: 3D Circuits and Power Circuits
Chair: Mohamad Hammam Alsafrjalani
 
Gate-Level Models for Fast Cross-Level Power Density Estimation
Philipp Schlicker and Oliver Bringmann
 
Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology
Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed Sabry and David Atienza
 
Cost Modeling and Analysis of TSV and Contactless 3D-ICs
Minmin Jiang and Vasileios Pavlidis
 
A 53%-PTE and 4-Mbps Power and Data Telemetry Circuit based on Adaptive Duty-cycling BPSK Modulated Class-E Amplifier
Siyao Zhu, Jian Zhao, Yongfu Li and Mingyi Chen

Technical Session 10A

Friday
September 11
 
11:00 - 12:00
Tech session 10A: Microelectronic Systems Education Workshop
Chair: John Nestor
 
Teaching Cyber Physical System Co-design: IoT on an FPGA Approach
Youngsoo Kim
 
A Simplified ARM Processor for VLSI Education
(Best Paper Award)
David Harris, Noah Boorstin, Kaveh Pezeshki, Veronica Cortes and Shuojin Hang
 
A Board and Projects for an FPGA/Microcontroller-Based Embedded Systems Lab
Joshua Brake, David Harris, Kaveh Pezeshki, Caleb Norfleet, Erik Meike, Teerapat Jenrungrot and Matthew Spencer
 
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures
Jianlei Yang, Xiaopeng Gao and Weisheng Zhao
 
A New Silicon-aware Big Data SoC Timing Analysis Solution: A Case Study of Empyrean University Program
Han Yu, Chao Guo, Bin Chen, Changxin Du, Xiao Yong and Shenhua Dong

Special Session 1B

Tuesday
September 8
 
10:00 - 11:00
Special session 1B: Emerging Memory-Enabled Computing for Future Electronics
Chair: Xunzhao Yin
 
Reliable and Robust RRAM-based Neuromorphic Computing
Grace Li Zhang, Bing Li, Ying Zhu, Shuhang Zhang, Tianchen Wang, Yiyu Shi, Tsung-Yi Ho, Hai (Helen) Li and Ulf Schlichtmann
 
Modeling and benchmarking Computing-in-Memory for Design Space Exploration
"Dayane Reis, Di Gao, Shaahin Angizi, Xunzhao Yin, Deliang Fan, Michael Niemier, Cheng Zhuo and X. Sharon Hu
 
Accelerating Emerging Workloads with In-Memory-Computing
Zheyu Li, Nagadastagiri Challapalle, Akshay Krishna Ramanathan and Vijaykrishnan Narayanan
 
Deep Neural Network Accelerators with Spintronic Memories
He Zhang, Wang Kang, Jinyu Bai, Biao Pan and Weisheng Zhao

Special Session 2B

Tuesday
September 8
 
11:00 - 12:00
Special session 2B: In-Memory Computing for Advanced Machine Learning Applications: An EDA Perspective
Chair: Sai Manoj
 
Energy-Efficient Machine Learning Accelerator for Binary Neural Networks
Wei Mao, Zhihua Xiao, Peng Xu, Fengwei An and Hao Yu
 
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, X. Sharon Hu, Yu Cao, Yuan Xie, Yu Wang and Huazhong Yang
 
Cluster-Based Partitioning of Convolutional Neural Networks: A Solution for Computational Energy and Complexity Reduction
Ali Mirzaein, Masoud Pourreza, Mohammad Sabokrou, Ashkan Vakil, Houman Homayoun, Tinoosh Mohsenin and Avesta Sasan
 
A Review of In-Memory Computing Architectures for Machine Learning Applications
Sathwika Bavikadi, Purab Sutradhar, Khaled, Khaswaneh, Amlan Ganguly and Sai Manoj P D

Special Session 3B

Wednesday
September 9
 
08:00 - 09:00
Special session 3B: Efficient and Secure Deep Learning and Reinforcement Learning in Embedded Systems
Chair: Yanzhi Wang
 
A Privacy-Preserving-Oriented DNN Pruning and Mobile Acceleration Framework
Yifan Gong, Zheng Zhan, Zhengang Li, Wei Niu, Bin Ren, Xiaolong Ma, Wenhao Wang, Xiaolin Xu, Caiwen Ding, Xue Lin and Yanzhi Wang
 
Robust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness
Adnan Siraj Rakin, Zhezhi He, Li Yang, Yanzhi Wang, Liqiang Wang and Deliang Fan
 
An Energy Efficient Guided Reinforcement Learning Embedded Hardware Using Structured Language Constraints
Aidin Shiri, Bharat Prakash, Arnab Mazumder, Houman Homayoun, Avesta Sasan and Tinoosh Mohsenin
 
Learning Diverse Latent Representations for Improving the Resilience to Adversarial Attacks
Ali Mirzaeian, Mohammad Sabokrou, Mohammad Khalooei, Tinoosh Mohsenin, Jana Kosecka, Houman Homayoun and Avesta Sasan

Special Session 4B

Wednesday
September 9
 
10:00 - 11:00
Special session 4B: Advances in Microarchitecture Security: from Detection of Threats to Mitigation
Chair: Khaled Khasawneh
 
The Evolution of Transient-Execution Attacks
Claudio Canella, Behnam Omidi, Khaled N. Khasawneh and Daniel Gruss
 
Defenses Evolution against Transient Execution Attacks
Behnam Omidi, Claudio Canella, Daniel Gruss, Sai Manoj P D and Khaled N. Khasawneh
 
StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features
Hossein Sayadi, Yifeng Gao, Hosein Mohammadi Makrani, Tinoosh Mohsenin, Avesta Sasan, Setareh Rafatirad, Jessica Lin and Houman Homayoun
 
Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks
Han Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Tinoosh Mohsenin and Houman Homayoun

Special Session 5B

Wednesday
September 9
 
11:00 - 12:00
Special session 5B: Protecting the Hardware in the Manufacturing Supply Chain: A Special Session on Hardware Security
Chair: Hassan Salmani
 
Trust Issues in COTS: The Challenges and Emerging Solution
Tamzidul Hoque, Patanjali SLPSK and Swarup Bhunia
 
On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic
Hadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun and Avesta Sasan
 
A New Aging Sensor for the Detection of Recycled Ics
Zhichao Xu, Aijiao Cui and Gang Qu

Special Session 6B

Thursday
September 10
 
08:00 - 09:00
Special session 6B: When Energy Efficiency and Multi-level Interaction Work Together
Chair: Hao Cai
 
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device
Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang and Weisheng Zhao
 
In Memory Computing: The Next Generation AI Computing Paradigm
Yufei Ma, Yuan Du, Li Du, Jun Lin and Zhongfeng Wang
 
A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing
Bo Liu, Yan Li, Lepeng Huang, Hao Cai, Wentao Zhu, Shisheng Guo, Yu Gong and Zhen Wang
 
Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM
Shaahin Angizi, Wei Zhang and Deliang Fan

Special Session 7B

Thursday
September 10
 
10:00 - 11:00
Special session 7B: Security in/for Approximate Computing
Chair: Chongyan Gu
 
Security analysis of hardware Trojans on Approximate Circuits
Yuqin Dou, Chongyan Gu, Chenghua Wang, Weiqiang Liu and Maire O'Neill
 
Side Channel Attacks vs Approximated Computing
Francesco Regazzoni and Ilia Polian
 
Blurring Boundaries: A New Way to Secure Approximate Computing Systems
Pruthvy Yellu, Landon Buell, Dongpeng Xu and Qiaoyan Yu
 
Is It Approximate Computing or Malicious Computing?
Ye Wang, Jian Dong, Qian Xu, Zhaojun Lu and Gang Qu

Panel Session 1

Thursday
September 10
 
11:00 - 12:00
Panel 1: Cross-Layer Design of Cyber-Physical Systems: from Circuit to Cloud
Chair: Wanli Chang
 
AxR-NN: Approximate Computation Reuse for Energy-Efficient Convolutional Neural Networks
Dongning Ma, Xunzhao Yin, Michael Niemier, X. Sharon Hu and Xun Jiao
 
Design Insights of Non-volatile Processors and Accelerators in Energy Harvesting Systems
Keni Qiu, Mengying Zhao, Zhenge Jia, Jingtong Hu, Chun Jason Xue, Kaisheng Ma, Xueqing Li, Yongpan Liu and Vijaykrishnan Narayanan
 
Dual-Plane Time-Triggered Ethernet Switch Architecture
Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin and Jianlei Yang
 
Fast Consistency Auditing for Massive Industrial Data in Untrusted Cloud Services
Jingxian Cheng, Saiyu Qi, Wenqing Wang, Yuchen Yang and Yong Qi

Panel Session 2

Friday
September 11
 
10:00 - 11:00
Panel 2: Security and Privacy Issues in AI and Their Impacts on Hardware Security
Chair: Jiliang Zhang
 
Privacy Threats and Protection in Machine Learning
Jiliang Zhang, Chen Li, Jing Ye and Gang Qu
 
Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs
Qingli Guo, Jing Ye, Jiliang Zhang, Yu Hu, Xiaowei Li and Huawei Li
 
On Configurable Defense against Adversarial Example Attacks
Bo Luo, Min Li, Yu Li and Qiang Xu
 
Adversarial Perturbation with ResNet
Heng Liu, Linzhi Jiang, Jian Xu, Dexin Wu and Liqun Chen

Poster session 1

Friday
September 11
 
08:00 - 09:00
Chair: Soheil Salehi
 
Litho-NeuralODE: Improving Hotspot Detection Accuracy with Advanced Data Augmentation and Neural Ordinary Differential Equations
Wei Lu, Yuhang Zhang, Qing Zhang, Xinjie Zhang and Yongfu Li
 
A Constraint-Driven Compact Model with Partition Strategy for Ordered Escape Routing
Zhaopo Liao and Sheqin Dong
 
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength
Wei Wang, Vasileios Pavlidis and Yuanqing Cheng
 
Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning
Lorenzo Servadei, Edoardo Mosca, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker and Robert Wille
 
Latency Variation Aware Read Performance Optimization on 3D High Density NAND Flash Memory
Yina Lv, Liang Shi, Chun Jason Xue, Qingfeng Zhuge and Edwin Sha
 
HTcatcher: Finite State Machine and Feature Verifcation for Large-scale Neuromorphic Computing Systems
Guorong He, Chen Dong, Xing Huang, Wenzhong Guo, Ximeng Liu and Tsung-Yi Ho
 
A Hybrid Synthesis Methodology for Approximate Circuits
Muhammad Awais, Hassan Ghasemzadeh Mohammadi and Marco Platzner
 
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor
Segi Lee, Sugil Lee, Jongeun Lee, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong and Kee-Won Kwon
 
Efficient and Trusted Detection of Rootkit in IoT Devices via Offline Profiling and Online Monitoring
Xingbin Jiang, Michele Lora and Sudipta Chattopadhyay
 
Quantitatively Assessing the Cyber-to-Physical Risk of Industrial Cyber-Physical Systems
Lingxuan Zhang, Linsen Li, Futai Zou and Jiachao Niu

Poster session 2

Friday
September 11
 
08:00 - 09:00
Chair:
 
SERN: Modeling and Analyzing the Soft Error Reliability of Convolutional Neural Networks
Liqi Ping, Jingweijia Tan and Kaige Yan
 
Defect-Tolerant Mapping of CMOL Circuits with Delay Optimization
Xiaojing Zha and Yinshui Xia
 
Multi–task Scheduling for PIM-based Heterogeneous Computing System
Dawen Xu, Cheng Chu, Cheng Liu, Ying Wang, Xianzhong Zhou, Lei Zhang, Huaguo Liang and Huawei Li
 
An ASIP approach to path allocation in TDM NoCs using adaptive search region
Seungseok Nam, Emil Matus and Gerhard Fettweis
 
Analog Circuit Implementation of LIF and STDP Models for Spiking Neural Networks
Zhitao Yang, Yucong Huang, Jianghan Zhu and Terry Tao Ye
 
DA-GC: A Dynamic Adjustment Garbage Collection Method ConsideringWear-leveling for SSD
Zhe Chen and Yuelong Zhao
 
Accelerating RRT Motion Planning Using TCAM
Yuxin Yang, Shiqi Lian, Xiaoming Chen and Yinhe Han
 
Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors
Chirag Joshi, Palash Das, Ashwini Kulkarni and Hemangee K. Kapoor
 
Analog Circuit Implementation of Neurons with Multiply-Accumulate and ReLU Functions
Yucong Huang, Zhitao Yang, Jianghan Zhu and Terry Tao Ye

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GLSVLSI 2020 Webmaster
Yi-Chung Chen (ychen@tnstate.edu), Tennessee State University.