GLSVLSI 2016 Accepted Papers

Mohamad Hammam Alsafrjalani and Ann Gordon-Ross. Dynamic Cache Tuning in Consumer-based Embedded Devices
Xiaotao Jia, Yici Cai, Qiang Zhou and Bei Yu. A Redundant Via Insertion Enhanced Concurrent Detailed Router
Hang Zhang, Xuhao Chen, Nong Xiao, Zhiguang Chen and Fang Liu. Red-Shield: Shielding Read Disturbance for STT-RAM Based Register files on GPUs
Hu Qingda, Sun Guangyu, Shu Jiwu and Zhang Chao. Exploring Main Memory Design based on Racetrack Memory Technology
Jiachen Song, Xi Li, Beilei Sun, Zhinan Cheng, Chao Wang and Xuehai Zhou. FCM: Towards Fine-Grained GPU Power Management for Closed Source Mobile Games
Tosiron Adegbija. Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems
Yong Chen, Emil Matus and Gerhard Fettweis. Trellis-search based Dynamic Multi-Path Connection Allocation for TDM-NoCs
Mohsen Imani, Shruti Patil and Tajana Rosing. DCC: Double Capacity Cache for Narrow-Width Data Values
Anastasios Psarras, Junghee Lee, Pavlos Mattheakis, Chrysostomos Nicopoulos and Giorgos Dimitrakopoulos. A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors
Zhezhao Xu, Wenjian Yu, Chao Zhang, Bolong Zhang, Meijuan Lu and Michael Mascagni. A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen Design
Tuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal and Jacob Mathews. Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths
Chaohui Du, Guoqiang Bai and Xingjun Wu. High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems
Rui Zhou and Weikang Qian. A General Sign Bit Error Correction Scheme for Approximate Adders
Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto and Takashi Sato. Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation
Andrea Calimera, Valerio Tenace and Enrico Macii. Graphene-PLA (GPLA): a compact and ultra-low power logic array architecture
Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor and Zeljko Zilic. Capturing true workload dependency of BTI-induced degradation in CPU components
Jaya Dofe, Hailang Wang, Emre Salman and Qiaoyan Yu. Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs
Pietro Mercati, Mohsen Imani, Francesco Paterna, Andrea Bartolini, Luca Benini and Tajana Rosing. VarDroid: Online Variability Emulation in Android/Linux Platforms
Jaeyoung Park and Michael Orshansky. Multiple Attempt Write Strategy for Low Energy STT-RAM
Kyle Juretus and Ioannis Savidis. Reduced Overhead Gate Level Logic Encryption
Yu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin and Chia-Hsin Lee. A New Methodology for Noise Sensor Placement Based on Association Rule Mining
Amr Tosson, Adam Neale, Mohab Anis and Lan Wei. 8T1R: A Novel Low-power High-Speed RRAM-based Non-volatile SRAM Design
Mohammad Motamedi, Philipp Gysel and Soheil Ghiasi. To Reconfigure or Not to Reconfigure: The Case of FPGA-Based Convolutional Neural Network Acceleration
Amr Tosson, Lan Wei and Mohab Anis. RRAM Refresh Circuit: A Proposed Solution To Resolve The Soft-Error Failures For HfO2/Hf 1T1R RRAM Memory Cell
Deliang Fan. Ultra-Low Energy Reconfigurable Spintronic Threshold Logic Gate
Sita Kondamadugula and Srinath R Naidu. Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization
Chen Yang, Yan Li, Wei Zhong and Song Chen. Real-Time Stereo Matching Using Guided Image Filter
Daniele Jahier Pagliari, Enrico Macii and Massimo Poncino. Approximate Differential Encoding for Energy-Efficient Serial Communication
Yukai Chen, Sara Vinco, Enrico Macii and Massimo Poncino. Fast Thermal Simulation using SystemC/AMS
Vijeta Rathore, Vivek Chaturvedi and Thambipillai Srikanthan. Performance Constraint-Aware Task Mapping to Optimize Lifetime Reliability of Manycore Systems
Govinda Sannena and Bishnu Prasad Das. A Metastability Immune Timing Error Masking Flip-Flop for Dynamic Variation Tolerance
Yu Bai and Mingjie Lin. Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices
Saman Kiamehr, Mojtaba Ebrahimi and Mehdi. B. Tahoori. Temperature-aware Dynamic Voltage Scaling for Near-Threshold Computing
Ioannis Papistas and Vasilis Pavlidis. Inter-Tier Crosstalk Noise on Power Delivery Networks for 3-D ICs with Inductively-Coupled Interconnects
Ralph Nyberg, Dietmar Heinz, Johann Heyszl and Georg Sigl. Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation
Sparsh Mittal and Jeffrey Vetter. Reducing Soft-error Vulnerability of Caches using Data Compression
Rajendra Bishnoi, Fabian Oboril and Mehdi Tahoori. Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices
Qin Xiong, Zhonghai Lu, Fei Wu and Changsheng Xie. Real-Time Analysis for Wormhole NoC: Revisited and Revised
Bo Yuan, Yanzhi Wang and Zhongfeng Wang. Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing
Sara Vinco, Yukai Chen, Enrico Macii and Massimo Poncino. A Unified Model of Power Sources for the Simulation of Electrical Energy Systems
Ali Alsuwaiyan and Kartik Mohanram. An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories
Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He and Yuchun Ma. Modular Placement for Interposer based Multi-FPGA Systems
Morteza Soltani, Mohammad Ebrahimi, Rasool Sharifi and Zain Navabi. Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping
Munish Jassi, Uzair Sharif, Daniel Müller-Gritschneder and Ulf Schlichtmann. Hardware-Accelerated Software Libraries Drivers Generation for IP-Centric SoC Designs
Marcelo Ruaro and Fernando Gehm Moraes. Dynamic Real-Time Scheduler for Large-Scale MPSoCs
Naman Saraf and Kia Bazargan. Polynomial Arithmetic Using Sequential Stochastic Logic
Cosimo Aprile, Luca Baldassarre, Vipul Gupta, Juhwan Yoo, Mahsa Shoaran, Yusuf Leblebici and Volkan Cevher. Learning Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signals Acquisition
Yongsuk Choi and Yong-Bin Kim. A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC
Xijing Han, Marco Donato, Iris Bahar, Alexander Zaslavsky and William Patterson. Design of Error-Resilient Logic Gates with Reinforcement Using Implications
Aditya Dalakoti, Carrie Segal, Merritt Miller and Forrest Brewer. Asynchronous High Speed Serial Links Analysis using Integrated Charge for Event Detection
Keshab Parhi and Yin Liu. Computing Complex Functions using Factorization in Unipolar Stochastic Logic
Xiaolin Xu and Daniel Holcomb. A Clockless Sequential PUF with Autonomous Majority Voting
Amey Kulkarni, Tahmid Abtahi, Emily Smith and Tinoosh Mohsenin. Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration
Divya Pathak, Mohammad Hajkazemi, Mohammad Tavana, Houman Homayoun and Ioannis Savidis. Load Balanced On-Chip Power Delivery for Average Current Demand
Hassan Afzali-Kusha, Alireza Shafaei and Massoud Pedram. Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry
Pei Luo, Cheng Li and Yunsi Fei. Concurrent Error Detection for Reliable SHA-3 Design
Travis Boraten, Avinash Kodi and Dominic Ditomaso. Secure Model Checkers for Network-on-Chip (NoC) Architectures
Vincent Mirian and Paul Chow. Extracting Designs of Secure IPs using FPGA CAD Tools
Adam Page, Nasrin Attaran, Colin Shea, Houman Homayoun and Tinoosh Mohsenin. Low-Power ManyCore Accelerator for Personalized Biomedical Applications
Xueyan Wang, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao and Gang Qu. Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers
Poorna Marthi, Sheikh Rufsan Reza, Nazir Hossain, Jean Francois Millithaler, Ignacio Iñiguez-De-La-Torre, Javier Mateos, Thomas Gonzalez and Martin Margala. Modeling and Study of Two-BDT-Nanostructure based Sequential Logic Circuits
Fabrizio Lombardi, Jie Han and Salin Junsangsri. A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File
Fabrizio Lombardi, Kazuteru Namba and Wei Wei. Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level
Ravi Patel, Eby Friedman and Praveen Raghavan. Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs
Md Farhadur Reza, Dan Zhao and Hong-Yi Wu. Task-Resource Co-allocation For Hotspot Minimization in Many-core NoCs
Hamed Tabkhi, Majid Sabbagh and Gunar Schirner. Guiding Power/Quality Exploration for Communication-Intense Stream Processing
Nidhi Batra, Pawan Sehgal, Shashwat Kaushik, Mohammad S. Hashmi and Anuj Grover. Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques
Subrata Das, Soma Das, Adrija Majumdar, Parthasarathi Dasgupta and Debesh Kumar Das. Delay estimates for Graphene nanoribbons: a novel measure of fidelity and experiments with global routing trees
Jordi Pérez-Puigdemont and Francesc Moll. ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system
Ning Liu, Caiwen Ding, Yanzhi Wang and Jingtong Hu. Neural Network-based Prediction Algorithms for In-Door Multi-Source Energy Harvesting System for Non-Volatile Processors
Adam Watkins and Spyros Tragoudas. An Enhanced Analytical Electrical Masking Model for Multiple Event Transients
Daniel Kumar and Hae-Seung Lee. A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs