|
Tuesday 5/19/2015 |
19:00 |
Welcome Reception -- City Center A |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Wednesday 5/20/2015 |
|
Session A |
Session B |
8:30 |
Registration / Welcome -- Grand Ballroom Foyer |
|
9:00 |
Opening & Keynote I -- Grand Ballroom 4, 5, & 6 |
|
Chairs: Alex Jones and Hai (Helen) Li, University of
Pittsburgh |
|
|
|
Speaker: Krishnendu Chakrabarty, Duke University |
|
|
|
Digital Microfluidic Biochips: Towards Functional
Diversity, More than Moore, and Cyberphysical
Integration |
|
|
|
|
10:30 |
Coffee Break -- Grand Ballroom Foyer |
|
Reliability, Resiliency, Robustness I -- Grand Ballroom
4 |
CAD for New Technologies -- Grand Ballroom 5 & 6 |
|
Session Chair:
Fabrizio Lombardi, Northeastern
University |
Session Chair: C.Y. Roger Chen, Syracuse University |
|
|
|
10:45 |
7 |
(L) |
Nima Aghaee, Zebo Peng and Petru Eles. Efficient Test
Application for Rapid Multi-Temperature Testing |
26 |
(L) |
Tiantao Lu and Ankur Srivastava. Electromigration-aware
Clock Tree Synthesis for TSV-based 3D-Ics |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
11:15 |
120 |
(L) |
Dimitra Papagiannopoulou, Andrea Marongiu, Tali
Moreshet, Luca Benini, Maurice Herlihy and Iris
Bahar. Playing with Fire: Transactional Memory Revisited
for Error-Resilient and Energy-Efficient MPSoC Execution |
131 |
(L) |
Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian
and Massoud Pedram. Layout Characterization and Power
Density Analysis for Shorted-Gate and Independent-Gate
7nm FinFET Standard Cells |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
11:45 |
27 |
(S) |
Fatemeh Tehranipoor, Nima Karimian, Kan Xiao and John
Chandy. DRAM based Intrinsic Physical Unclonable
Functions for System Level Security |
157 |
(S) |
Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo
Poncino, Valerio Tenace, Giovanni De Micheli and
Pierre-Emmanuel Gaillardon. Exploiting the Expressive
Power of Graphene Reconfigurable Gates via
Post-Synthesis Optimization |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12:00 |
39 |
(S) |
Songwei Pei, Jingdong Zhang, Yu Jin, Song Jin, Jun Liu
and Weizhi Xu. An Effective TSV Self-Repair Scheme for
3D-Stacked Ics |
12 |
(S) |
Marco Donato, Iris Bahar, William Patterson and
Alexander Zaslavsky. A Simulation Framework for
Analyzing Transient Effects Due to Thermal Noise in
Sub-Threshold Circuits |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12:15 |
Lunch -- Marquis Ballroom A & B |
|
Best Paper Session -- Grand Ballroom
4, 5, & 6 |
|
Session Chair: Martin Margala, University of
Massachusetts, Lowell |
13:30 |
5 |
(L) |
Fabrizio Lombardi, Jie Han, Linbin Chen and Weiqiang
Liu. Design of Approximate Unsigned Integer
Non-restoring Divider for Inexact Computing |
|
|
|
|
|
|
|
14:00 |
76 |
(L) |
Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H.
Meyer, Dimitrios Soudris, Francky Catthoor and Zeljko
Zilic. Efficient Reliability Analysis of Processor
Datapath using Atomistic BTI Variability Models |
|
|
|
|
14:30 |
16 |
(L) |
Sai Vineel Reddy Chittamuru, Srinivas Desai and Sudeep
Pasricha. A Reconfigurable Silicon-Photonic Network with
Improved Channel Sharing for Multicore Architectures |
|
|
|
|
|
|
|
15:00 |
68 |
(L) |
Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang,
Weisheng Zhao, Pierre Chor-Fung Chia and Hai Li. A
High-Speed Robust NVM-TCAM Design Using Body Bias
Feedback |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15:30 |
Coffee Break -- Grand Ballroom Foyer |
15:45 |
Poster Session 1 -- Grand Ballroom Foyer |
|
Session Chair: Tali Moreshet, Boston University |
|
54 |
|
Yukai Chen, Andrea Calimera, Massimo Poncino and Enrico
Macii. Characterizing the Activity Factor in NBTI Aging
Models for Embedded Cores |
6 |
|
Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran
Singh, Santosh Kumar Vishvakarma and Devesh
Dwivedi. Dataline Isolated Differential Current
Feed/Mode Sense Amplifier for Small Icell SRAM Using
FinFET |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
63 |
|
Yue Ma, Thidapat Chantem, Robert P. Dick and X. Sharon
Hu. Improving Lifetime of Multicore Real-Time Systems
through Global Utilization Control |
140 |
|
Ibtissem Seghaier, Mohamed H. Zaki and Sofiene
Tahar. Statistically Validating the Impact of Process
Variations on Analog and Mixed Signal Designs |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
70 |
|
Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, Moshe Preil, Azat
Latypov and David Z. Pan. Directed Self-Assembly Based
Cut Mask Optimization for Unidirectional Design |
20 |
|
Dilip Vasudevan and Andrew Chien. The Bit-Nibble-Byte
MicroEngine (BnB) for Efficient Computing on Short Data |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
132 |
|
Subhendu Roy, Pavlos M Mattheakis, Peter S Colyer,
Laurent Masse-Navette, Pierre-Olivier Ribet and David Z
Pan. Skew Bounded Buffer Tree Resynthesis for Clock
Power Optimization |
45 |
|
Bo Yuan and Keshab K Parhi. Reduced-latency LLR-based SC
List Decoder for Polar Codes |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
|
Fabrizio Lombardi, Wei Wei and Kazuteru Namba. Novel
Designs of Embedded Hybrid Cells for High Performance
Memory Circuits |
136 |
|
Monther Abusultan and Sunil Khatri. Delay, Power and
Energy Tradeoffs in Deep Voltage-scaled FPGAs |
|
|
|
|
|
|
|
|
Energy Efficient Systems -- Grand Ballroom 4 |
Interconnects and NoCs -- Grand Ballroom 5 & 6 |
|
Session Chair: Baris Taskin, Drexel University |
Session Chair: Miroslav Velev, Aries Design Corporation |
|
|
|
16:15 |
65 |
(L) |
Tosiron Adegbija and Ann Gordon-Ross. Phase-based Cache
Locking for Embedded Systems |
107 |
(L) |
Sourav Das, Dongjin Lee, Daehyun Kim and Partha
Pande. Small-World Network Enabled Energy Efficient and
Robust 3D NoC Architectures |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
16:45 |
103 |
(L) |
Dharanidhar Dang, Biplab Patra and Rabi Mahapatra. A
Multilayered Design Approach for Efficient Hybrid 3D
Photonics Network-on-chip |
100 |
(L) |
Alexandre Briere, Eren Unlu, Julien Denoulet, Andrea
Pinna, Bertrand Granado, Francois Pecheux, Yves Louet
and Christophe Moy. A Dynamically Reconfigurable RF NoC
for Many-Core |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
17:15 |
145 |
(S) |
Alireza Shafaei Bejestan, Yanzhi Wang, Srikanth
Ramadurgam, Yuankun Xue, Paul Bogdan and Massoud
Pedram. Analyzing the Dark Silicon Phenomenon in a
Many-Core Chip Multi-Processor under Deeply-Scaled
Process Technologies |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
19:00 |
Gala Dinner & Keynote -- Marquis Ballroom A & B |
|
|
Chair: Alex Jones, University of Pittsburgh |
|
Erik Brunvand, University of Utah |
|
Computational Thinking Meets Design Thinking:
Technology and Arts Collaborations |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Thursday 5/21/2015 |
|
Session A |
Session B |
9:00 |
Keynote II -- Grand Ballroom 4, 5, & 6 |
|
Chair: Alex Jones, University of Pittsburgh |
|
Zhenqiang Ma, University of Wisconsin, Madison |
|
Graphene neural sensors for next generation in vivo
imaging and optogenetics |
10:00 |
Coffee Break -- Grand Ballroom Foyer |
|
Reliability, Resiliency, Robustness II -- Grand Ballroom
4 |
VLSI Design -- Grand Ballroom 5 & 6 |
|
Session Chair: Sorin Cotofana, Delft University of
Technology |
Session Chair: Emre Salman, Stony Brook University |
|
|
|
10:30 |
154 |
(L) |
Amir Yazdanbakhash, David Palframan, Azadeh Davoodi, Nam
Sung Kim and Mikko Lipasti. Online and Operand-Aware
Detection of Failures Utilizing False Alarm Vectors |
1 |
(L) |
Anirban Sengupta and Saumya Bhadauria. Untrusted Third
Party Digital IP cores: Power-Delay Trade-off Driven
Exploration of Hardware Trojan Secured Datapath during
High Level Synthesis |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
11:00 |
93 |
(L) |
Mehdi Sadi, Xiaoxiao Wang, Leroy Winemberg and Mark
Tehranipoor. Speed Binning using Machine Learning and
On-chip Slack Sensors |
11 |
(L) |
Samira Ataei and James E. Stine. Multi Replica Bitline
Delay Technique for Variation Tolerant Timing of SRAM
Sense Amplifiers |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
11:30 |
124 |
(S) |
Michail Mavropoulos, Georgios Keramidas, Grigorios
Adamopoulos and Dimitris Nikolos. Reconfigurable - Self
Adaptive Fault Tolerant Cache Memory for DVS enabled
Systems |
112 |
(S) |
Donald Kline, Kai Wang, Rami Melhem and Alex
Jones. MSCS: Multi-hop Segmented Circuit Switching |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
11:45 |
Lunch -- Marquis Ballroom A & B |
|
Special Session 1 -- Grand Ballroom 4 |
Special Session 2 -- Grand Ballroom 5 & 6 |
|
Neuromorphic Computing based on Resistive Devices |
Advances in Neuromorphic Architectures and Future
Applications |
|
Session Chair: Natasa Miskov-Zivanov, Carnegie Mellon
University |
Session Chair: Cyrille Chavet, Université de
Bretagne-Sud |
13:00 |
|
|
EDA Challenges for Memristor-Crossbar based
Neuro-morphic Computing |
|
|
Origami: A Convolutional Network Accelerator |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
13:25 |
|
|
Energy Efficient RRAM Spiking Neural Network for Real
Time Classification |
|
|
Restricted Clustered Neural Network for Storing Real
Data |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
13:50 |
|
|
On-chip Sparse Learning with Resistive Cross-point Array
Architecture |
|
|
NeuroDSP Accelerator for Face Detection Application |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
14:15 |
Coffee Break -- Grand Ballroom Foyer |
14:30 |
Poster Session 2 -- Grand Ballroom Foyer |
|
Session Chair: Matthias Fuegger, Max Planck Institute |
|
35 |
|
Yong Li, Haifeng Xu, Rami Melhem and Alex Jones. Space
Oblivious Compression: Power Reduction for Non-Volatile
Main Memories |
60 |
|
Seyyed Hasan Mozafari, Kevin Skadron and Brett H.
Meyer. Yield-aware Performance-Cost Characterization for
Multi-Core SIMT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
53 |
|
Poovaiah Palangappa and Kartik
Mohanram. Flip-Mirror-Rotate: An Architecture for
Bit-write Reduction and Wear Leveling in Non-volatile
Memories |
137 |
|
Luke Murray and Sunil Khatri. An Efficient Approach to
Sample On-Chip Power Supplies |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
13 |
|
Joonho Kong, Arslan Munir and Farinaz
Koushanfar. Fine-Grained Voltage Boosting for Improving
Yield in Near-Threshold Many-Core Processors |
83 |
|
Thomas Marconi and Sorin Cotofana. Dynamic Bitstream
Length Scaling Energy Effective Stochastic LDPC Decoding |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
52 |
|
Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis,
Nicholas Axelos and Kiamal Pekmestzi. Approximate
Multiplier Architectures Through Partial Product
Perforation: Power-Area Tradeoffs Analysis |
116 |
|
Matthew Kennedy, Brian Neel and Avinash Kodi. Runtime
Power Reduction Techniques in On-Chip Photonic
Interconnects |
|
|
|
|
|
|
|
|
74 |
|
Rosario Distefano, Nicola Bombieri, Carlo Laudanna,
Franco Fummi and Rosalba Giugno. A SystemC Platform for
Signal Transduction Modelling and Simulation in Systems
Biology |
|
|
|
|
|
|
|
|
|
|
|
Emerging Technologies -- Grand Ballroom 4 |
CAD and Circuits I -- Grand Ballroom 5 & 6 |
|
Session Chair: Yiran Chen, University of Pittsburgh |
Session Chair:
Jie Han, University of Alberta |
|
|
|
15:30 |
159 |
(L) |
Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera,
Enrico Macii and Massimo Poncino. Design and
Characterization of Analog-to-Digital Converters using
Graphene PN-Junctions |
127 |
(L) |
Weicheng Liu, Emre Salman, Can Sitik and Baris
Taskin. Clock Skew Scheduling in the Presence of Heavily
Gated Clock Networks |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
16:00 |
4 |
(L) |
Fabrizio Lombardi, Pilin Junsangsri and Jie Han. A
Ternary Content Addressable Cell using a single Phase
Change Memory (PCM) |
105 |
(L) |
Wei Ye, Bei Yu, Yong-Chan Ban, Lars Liebmann and David
Z. Pan. Standard Cell Layout Regularity and Pin Access
Optimization Considering Middle-of-Line |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
16:30 |
55 |
(S) |
K M Mohsin and Ashok Srivastava. Characterization of
SWCNT Bundle Based VLSI Interconnect with Self-heating
Induced Scatterings |
43 |
(S) |
Hafiz Ul Asad and Kevin D. Jones. Inevitability of
Phase-locking in a Charge Pump Phase Lock Loop using
Deductive Verification |
|
|
|
|
|
|
|
16:45 |
113 |
(S) |
Yandan Wang, Wei Wen, Miao Hu and Hai Li. A Novel True
Random Number Generator Design Leveraging Emerging
Memristor Technology |
142 |
(S) |
Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik
and Baris Taskin. A Novel Static D Flip-Flop Topology
for Low Swing Clocking |
|
|
|
|
|
|
|
17:00 |
118 |
(S) |
Qiuwen Lou, Indranil Palit, Andras Horvath, X. Sharon
Hu, Michael Niemier and Joseph Nahas. TFET-based
Operational Transconductance Amplifier Design for CNN
Systems |
57 |
(S) |
Yaoqiang Li, Pierce I-Jen Chuang, Andrew Kennings and
Manoj Sachdev. Voltage-Boosted Synchronizers |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Friday 5/22/2015 |
8:45 |
Keynote III -- Grand Ballroom 4, 5 & 6 |
|
Chair: Martin Margala, University of Massachusetts,
Lowell |
|
|
Andrew Schwartz, University of Pittsburgh |
|
|
|
Recent Advances in Brain-controlled Prosthetics for
Paralysis |
9:45 |
Coffee Break -- Grand Ballroom Foyer |
|
Special Session 3 -- Grand Ballroom 4 |
Special Session 4 -- Grand Ballroom 5 & 6 |
|
Bio Design Automation |
Emerging Computing Paradigm for Error-Tolerant
Applications: Approximate Computing and Stochastic
Computing |
|
Session Chair: Yu Wang ,Tsinghua University |
Session Chair: Yiran Chen, University of Pittsburgh |
10:00 |
|
|
Formal Analysis Provides Parameters for Guiding
Hyperoxidation in Bacteria Using Phototoxic Proteins |
|
|
On the Functions Realized by Stochastic Computing
Circuits |
|
|
|
|
|
|
|
|
|
|
Design Automation for Biological Models: A Pipeline that
Incorporates Spatial and Molecular Complexity |
|
|
ApproxMA: Approximate Memory Access for Dynamic
Precision Scaling |
|
|
|
|
|
|
|
10:45 |
|
|
Mammalian Synthetic Gene Circuits |
|
|
A Comparative Review and Evaluation of Approximate
Adders |
|
|
|
|
|
|
|
|
|
|
Automation of Biological Model Learning, Design and
Analysis |
|
|
Minimizing Error of Stochastic Computation through
Linear Transformation |
|
|
|
|
|
|
|
11:30 |
Coffee Break -- Grand Ballroom Foyer |
|
Session A |
Session B |
|
CAD and Circuits II |
Power and Temperature-Aware Design |
|
Session Chair:Miroslav Velev, Aries Design Automation,
U.S.A. |
Session Chair: Bei Yu, University of Texas at Austin |
|
|
|
11:45 |
94 |
(L) |
Robert Najvirt, Matthias Függer, Thomas Nowak, Ulrich
Schmid, Michael Hofbauer and Kurt Schweiger. Experimental
Validation of a Faithful Binary Circuit Model |
175 |
(S) |
Ali Akbari, Hamid Noori, Saadat Pour Mozafari and Farhad
Mehdipour. Dynamic Task Priority Scaling for Thermal
Management of Multi-core Processors with Heavy Workload |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12:00 |
|
|
|
69 |
(S) |
Shiting Lu, Wayne Burleson and Russell Tessier. Reinforcement
learning for thermal-aware many-core task allocation |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12:15 |
133 |
(L) |
Jiani Xie and C.Y.Roger Chen. Lookup Table Based
Discrete Gate Sizing for Delay Minimization with
Modified Elmore Delay Model |
110 |
(S) |
Katayoun Neshatpour, Amin Khajeh Djahromi, Wayne
Burleson and Houman Homayoun. Revisiting Dynamic Thermal
Management Exploiting Inverse Thermal Dependence |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12:30 |
|
|
|
32 |
(S) |
Mohammad Hossein Hajkazemi, Michael Chorney, Reyhaneh
Jabbarvand Behrouz, Mohammad Khavari Tavana and Houman
Homayoun. Adaptive Bandwidth Management for
Performance-Temperature Trade-offs in Heterogeneous
HMC+DDRx Memory |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12:45 |
51 |
(S) |
Mineo Kaneko. A Novel Framework for Temperature
Dependence Aware Clock Skew Scheduling |
171 |
(S) |
Avijit Chakraborty and D. M. H. Walker. Optimizing VMIN
of ROM Arrays Without Loss of Noise Margin |
|
|
|
|
|
|
|
13:00 |
Closing Session -- Grand Ballroom 4, 5 & 6 |
|
Chairs: Alex Jones, Hai (Helen) Li, University of
Pittsburgh |
|
(Lunch boxes to be provided) |